Journal: IEEE Transactions on Circuits and Systems II. Express Briefs

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IEEE

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1549-7747
1057-7130
1558-3791
1558-125X

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Publications 1 - 10 of 25
  • A Frequency-Domain Analysis of Latch Comparator Offset due to Load Capacitor Mismatch
    Item type: Journal Article
    Tao, Yonghong; Hierlemann, Andreas; Lian, Yong (2015)
    IEEE Transactions on Circuits and Systems II. Express Briefs
  • Nonlinear discrete-time analysis of the fixed frequency switch-mode DC-Dc converters dynamics
    Item type: Journal Article
    Papafotiou, G.A.; Margaris, N.I. (2005)
    IEEE Transactions on Circuits and Systems II. Express Briefs
  • CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices
    Item type: Journal Article
    Capotondi, Alessandro; Rusci, Manuele; Fariselli, Marco; et al. (2020)
    IEEE Transactions on Circuits and Systems II. Express Briefs
  • A Neuromorphic Computational Primitive for Robust Context-Dependent Decision Making and Context-Dependent Stochastic Computation
    Item type: Journal Article
    Liang, Dongchen; Indiveri, Giacomo (2019)
    IEEE Transactions on Circuits and Systems II. Express Briefs
  • A 46 Gbps 12 pJ/b Sparsity-Adaptive Beamspace Equalizer for mmWave Massive MIMO in 22FDX
    Item type: Journal Article
    Mirfarshbafan, Seyedhadi; Studer, Christoph (2024)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    We present a GlobalFoundries 22FDX FD-SOI application-specific integrated circuit (ASIC) of a beamspace equalizer for millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) systems. The ASIC implements a recently-proposed power-saving technique called sparsity-adaptive equalization (SPADE). SPADE exploits the inherent sparsity of mmWave channels in the beamspace domain to reduce the dynamic power of matrix-vector products by skipping multiplications for which the magnitude of both operands are below pre-defined thresholds. Simulations with realistic mmWave channels show that SPADE incurs less than 0.7 dB SNR degradation at 1% target bit error rate compared to antenna-domain equalization. ASIC measurement results demonstrate an equalization throughput of 46 Gbps and show that SPADE offers up to 38% power savings compared to antenna-domain equalization. A comparison with state-of-the-art massive MIMO equalizer designs reveals that our ASIC achieves superior normalized energy efficiency.
  • On Resistive Networks of Constant-Power Devices
    Item type: Journal Article
    Simpson-Porco, John W.; Dörfler, Florian; Bullo, Francesco (2015)
    IEEE Transactions on Circuits and Systems II. Express Briefs
  • Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In
    Item type: Journal Article
    Ottaviano, Alessandro; Benz, Thomas; Scheffler, Paul; et al. (2023)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    Power and cost constraints in the Internet-of-Things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous architectures. These designs use energy-efficient application-class host processors to coordinate compute-specialized multicore accelerators, amortizing the architectural costs of operating system support and external communication. This brief presents Cheshire, a lightweight and modular 64-bit Linux-capable host platform designed for the seamless plug-in of domain-specific accelerators. It features a unique low-pin-count DRAM interface, a last-level cache configurable as scratchpad memory, and a DMA engine enabling efficient data movement to or from accelerators or DRAM. It also provides numerous optional IO peripherals including UART, SPI, I2C, VGA, and GPIOs. Cheshire’s synthesizable RTL description, comprising all of its peripherals and its fully digital DRAM interface, is available free and open-source. We implemented and fabricated Cheshire as a silicon demonstrator called Neo in TSMC’s 65nm CMOS technology. At 1.2V, Neo achieves clock frequencies of up to 325 MHz while not exceeding 300 mW in total power on data-intensive computational workloads. Its RPC DRAM interface consumes only 250 pJ/B and incurs only 3.5 kGE in area for its PHY while attaining a peak transfer rate of 750 MB/s at 200 MHz.
  • Fast, Analytical Method for Structured Identification of SISO RC-Ladder-Type Systems
    Item type: Journal Article
    Hannigan, Brett C.; Menon, Carlo (2024)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    Structured system identification often requires solving optimization problems that are not deterministic in computation time and may converge to a local optimum. For the case of systems that can be represented as a SISO “RC-ladder” impedance network, this brief presents a closed-form algorithm that can determine the structured state-space matrices and extract the parameters from an arbitrarily transformed system, such as that produced by subspace system identification. This algorithm relies on a modified version of the Lanczos tridiagonalization process and the solving of a least squares problem with dimension equal to the system order. It is fast, deterministic, and successful for systems of low to moderate order. Practical applications include network synthesis, thermal model identification, and distributed sensing reconstruction, where exact RC parameter values must be identified from data.
  • High-Bandwidth Spatial Equalization for mmWave Massive MU-MIMO With Processing-in-Memory
    Item type: Journal Article
    Castañeda Fernández, Oscar; Jacobsson, Sven; Durisi, Giuseppe; et al. (2020)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    All-digital basestation (BS) architectures enable superior spectral efficiency compared to hybrid solutions in massive multi-user MIMO systems. However, supporting large bandwidths with all-digital architectures at mmWave frequencies is challenging as traditional baseband processing would result in excessively high power consumption and large silicon area. The recently-proposed concept of finite-alphabet equalization is able to address both of these issues by using equalization matrices that contain low-resolution entries to lower the power and complexity of high-throughput matrix-vector products in hardware. In this brief, we explore two different finite-alphabet equalization hardware implementations that tightly integrate the memory and processing elements: (i) a parallel array of multiply-accumulate (MAC) units and (ii) a bit-serial processing-in-memory (PIM) architecture. Our all-digital VLSI implementation results in 28nm CMOS show that the bit-serial PIM architecture reduces the area and power consumption up to a factor of 2x and 3x, respectively, when compared to a parallel MAC array that operates at the same throughput.
  • A Multi-Memristive Unit-Cell Array With Diagonal Interconnects for In-Memory Computing
    Item type: Journal Article
    Khaddam-Aljameh, Riduan; Martemucci, Michele; Kersting, Benedikt; et al. (2021)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    Memristive crossbar arrays can be used to realize matrix-vector multiplication (MVM) operations in constant time complexity by exploiting the Kirchhoff's circuit laws. This is enabled by the parallel read of the entire array in a single time step. However, parallel writing is prohibitive in such arrays due to limitations on the current that could be accumulated along the wires. Hence, loading the matrix elements into such an array still incurs significant time penalty. Another key challenge is the achievable computational precision. To overcome these challenges, we propose a unit-cell array design where each unit-cell comprises four memristive devices each attached to a selection transistor. Moreover, the array is organized in such a way that the selection transistors can be turned on in a diagonal fashion. We experimentally demonstrated this concept by fabricating a 2 x 2 unit-cell array based on projected phase-change memory (PCM) devices in 90 nm CMOS technology. It is shown that using the diagonal connections, the write operations can be parallelized while maintaining the current limit of the back-end-of-the-line metallization. Moreover, the increase in write time due to having more devices per unit-cell is minimized through a combination of single-shot and iterative programming schemes. Finally, we present experimental results on MVM operations that demonstrate improved computational precision exceeding that of a 4-bit fixed-point implementation.
Publications 1 - 10 of 25