Journal: IEEE Transactions on Circuits and Systems II. Express Briefs

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IEEE

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1549-7747
1057-7130
1558-3791
1558-125X

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Publications1 - 10 of 28
  • Energy Efficient In-Memory Hyperdimensional Encoding for Spatio-Temporal Signal Processing
    Item type: Journal Article
    Karunaratne, Geethan; Le Gallo, Manuel; Hersche, Michael; et al. (2021)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    The emerging brain-inspired computing paradigm known as hyperdimensional computing (HDC) has been proven to provide a lightweight learning framework for various cognitive tasks compared to the widely used deep learning-based approaches. Spatio-temporal (ST) signal processing, which encompasses biosignals such as electromyography (EMG) and electroencephalography (EEG), is one family of applications that could benefit from an HDC-based learning framework. At the core of HDC lie manipulations and comparisons of large bit patterns, which are inherently ill-suited to conventional computing platforms based on the von-Neumann architecture. In this work, we propose an architecture for ST signal processing within the HDC framework using predominantly in-memory compute arrays. In particular, we introduce a methodology for the in-memory hyperdimensional encoding of ST data to be used together with an in-memory associative search module. We show that the in-memory HDC encoder for ST signals offers at least 1.80× energy efficiency gains, 3.36× area gains, as well as 9.74× throughput gains compared with a dedicated digital hardware implementation. At the same time it achieves a peak classification accuracy within 0.04% of that of the baseline HDC framework.
  • Kinetic AC/DC Converter for Electromagnetic Energy Harvesting in Autonomous Wearable Devices
    Item type: Journal Article
    Bolt, Robin; Magno, Michele; Burger, Thomas; et al. (2017)
    IEEE Transactions on Circuits and Systems II. Express Briefs
  • Scaling Limits of Memristor-Based Routers for Asynchronous Neuromorphic Systems
    Item type: Journal Article
    Chen, Junren; Yang, Siyao; Wu, Huaqiang; et al. (2024)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    Multi-core neuromorphic systems typically use on-chip routers to transmit spikes among cores. These routers require significant memory resources and consume a large part of the overall system’s energy budget. A promising alternative approach to using standard CMOS and SRAM-based routers is to exploit the features of memristive crossbar arrays and use them as programmable switch-matrices that route spikes. However, the scaling of these crossbar arrays presents physical challenges, such as “IR drop” on the metal lines due to the parasitic resistance, and leakage current accumulation on multiple active memristors in their “off” state. While reliability challenges of this type have been extensively studied in synchronous systems for compute-in-memory matrix-vector multiplication (MVM) accelerators and storage class memory, little effort has been devoted so far to characterizing the scaling limits of memristor-based crossbar routers. Here, we study the challenges of memristive crossbar arrays, when used as routing channels to transmit spikes in asynchronous Spiking Neural Network (SNN) hardware. We validate our analytical findings with experimental results obtained from a 4K-ReRAM chip which demonstrates its functionality as a routing crossbar. We determine the functionality bounds on the routing due to the IR drop and leak problem, based on theoretical modeling, circuit simulations for a 22 nm FDSOI technology, and experimental measurements. This work highlights the limitations of this approach and provides useful guidelines for engineering the memristor device properties in memristive crossbar routers for multi-core asynchronous neuromorphic systems.
  • Frequency Stabilization of a 100GHz VCO using Resonator-Locked Loops in CMOS 28nm
    Item type: Journal Article
    Ameri, Ali; Svelto, Filippo; Niknejad, Ali M. (2026)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    This brief presents a novel frequency-locking technique in which two off-tuned chopped active resonators define a reference frequency to which a 100GHz voltage-controlled oscillator (VCO) is locked. Deviations from the reference frequency result in a power imbalance between the resonator outputs. This imbalance is detected and used as an error signal to restore the VCO frequency to the reference point. The loop operates without frequency dividers and off-chip references. The implementation, fabricated in a CMOS 28nm process, achieves a close-in phase noise suppression of up to 5.6dB at -3dBm output power, consuming only 24mW.
  • Toward a Dynamic Closed-Loop Neuromorphic Trajectory Interpolation Model: Hardware Emulation and Software Simulation
    Item type: Journal Article
    Casanueva-Morato, Daniel; Wu, Chenxi; Indiveri, Giacomo; et al. (2025)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    Neuromorphic engineering aims to incorporate the computational principles found in animal brains into modern technological systems. Controllers for robotic arms targeting specific positions often fall short in executing dynamically smooth trajectories, exhibiting rather segmented, step-like motions. This brief presents a closed-loop neuromorphic control system for event-based robotic arms, emphasizing a dynamic approach to trajectory interpolation through hardware emulation and software simulation. Our model employs a Shifted Winner-Take-All spiking network to interpolate reference trajectories and a spiking comparator network to ensure trajectory continuity against real-time positions, closing the control loop dynamically. The model's implementation on various neuromorphic platforms highlights its flexibility and adaptability across distinct computational paradigms, such as analog hardware emulation and digital software simulation. Experimental results demonstrate the efficacy of the analog implementation in terms of robustness and energy efficiency, while the digital simulations produce precise and stable performance. These outcomes substantiate the model's capacity to enhance robotic trajectory control and lay the foundation for the development of future neuromorphic robotic control systems.
  • Nonlinear discrete-time analysis of the fixed frequency switch-mode DC-Dc converters dynamics
    Item type: Journal Article
    Papafotiou, G.A.; Margaris, N.I. (2005)
    IEEE Transactions on Circuits and Systems II. Express Briefs
  • High-Bandwidth Spatial Equalization for mmWave Massive MU-MIMO With Processing-in-Memory
    Item type: Journal Article
    Castañeda Fernández, Oscar; Jacobsson, Sven; Durisi, Giuseppe; et al. (2020)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    All-digital basestation (BS) architectures enable superior spectral efficiency compared to hybrid solutions in massive multi-user MIMO systems. However, supporting large bandwidths with all-digital architectures at mmWave frequencies is challenging as traditional baseband processing would result in excessively high power consumption and large silicon area. The recently-proposed concept of finite-alphabet equalization is able to address both of these issues by using equalization matrices that contain low-resolution entries to lower the power and complexity of high-throughput matrix-vector products in hardware. In this brief, we explore two different finite-alphabet equalization hardware implementations that tightly integrate the memory and processing elements: (i) a parallel array of multiply-accumulate (MAC) units and (ii) a bit-serial processing-in-memory (PIM) architecture. Our all-digital VLSI implementation results in 28nm CMOS show that the bit-serial PIM architecture reduces the area and power consumption up to a factor of 2x and 3x, respectively, when compared to a parallel MAC array that operates at the same throughput.
  • Spatial Memoization
    Item type: Journal Article
    Rahimi, Abbas; Benini, Luca; Gupta, Rajesh K. (2013)
    IEEE Transactions on Circuits and Systems II. Express Briefs
  • A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
    Item type: Journal Article
    Garofalo, Angelo; Ottaviano, Alessandro; Perotti, Matteo; et al. (2025)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    Next-generation mixed-criticality Systems-on-chip (SoCs) must execute mixed-criticality AI-enhanced sensor processing and control workloads, ensuring reliable and time-predictable execution of critical tasks while fitting within a sub-2W power envelope. To tackle these challenges, we present a 16nm, reliable, time-predictable heterogeneous SoC with multiple programmable accelerators. Within a 1.2W power envelope, the SoC integrates software-configurable hardware IPs to ensure predictable access to shared resources, such as the on-chip interconnect and memory system, leading to tight upper bounds on execution times of critical applications. To accelerate mission-critical AI, the SoC integrates a reliable multi-core accelerator achieving 304.9 GOPS peak performance at 1.6 TOPS/W energy efficiency. Non-critical, compute-intensive, floating-point workloads are accelerated by a vector cluster, achieving 1.1 TFLOPS/W and 106.8 GFLOPS/mm2.
  • A Multi-Memristive Unit-Cell Array With Diagonal Interconnects for In-Memory Computing
    Item type: Journal Article
    Khaddam-Aljameh, Riduan; Martemucci, Michele; Kersting, Benedikt; et al. (2021)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    Memristive crossbar arrays can be used to realize matrix-vector multiplication (MVM) operations in constant time complexity by exploiting the Kirchhoff's circuit laws. This is enabled by the parallel read of the entire array in a single time step. However, parallel writing is prohibitive in such arrays due to limitations on the current that could be accumulated along the wires. Hence, loading the matrix elements into such an array still incurs significant time penalty. Another key challenge is the achievable computational precision. To overcome these challenges, we propose a unit-cell array design where each unit-cell comprises four memristive devices each attached to a selection transistor. Moreover, the array is organized in such a way that the selection transistors can be turned on in a diagonal fashion. We experimentally demonstrated this concept by fabricating a 2 x 2 unit-cell array based on projected phase-change memory (PCM) devices in 90 nm CMOS technology. It is shown that using the diagonal connections, the write operations can be parallelized while maintaining the current limit of the back-end-of-the-line metallization. Moreover, the increase in write time due to having more devices per unit-cell is minimized through a combination of single-shot and iterative programming schemes. Finally, we present experimental results on MVM operations that demonstrate improved computational precision exceeding that of a 4-bit fixed-point implementation.
Publications1 - 10 of 28