IEEE Solid-State Circuits Letters

Journal: IEEE Solid-State Circuits Letters

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IEEE

ISSN

2573-9603

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Publications 1 - 10 of 18

A 2.3GHz Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators achieving 78.1% Efficiency in 22nm FDSOI CMOS
Novello, Alessandro; Atzeni, Gabriele; Cristiano, Giorgio; et al. (2021)
IEEE Solid-State Circuits Letters
This letter introduces a fully integrated DC-DC converter based on electromagnetically coupled class-D LC oscillators featuring on-chip stacked 8-shaped transformers in a 22nm FDSOI CMOS process. The GHz-range resonant frequency of the proposed converter enables high integration of the passive components, achieving up to 3.2W/mm2 power density. The on-chip 8-shaped stacked transformers reach 16.9 quality factor and 0.91 coupling coefficient, demonstrating 78.1% converter efficiency. Furthermore, the twisted nature of the 8-shaped transformers introduces a magnetic field cancellation mechanism that minimizes the parasitic coupling between the transformers, saving 25% area in one single converter unit and 47% in the converter array, with respect a spiral transformer implementation. In addition, the field intensity is reduced by 27dB outside of the transformer borders compared with a spiral implementation, which helps to mitigate issues such as parasitic magnetic coupling with neighbouring circuits and EMI.
Design Challenges of Fully Integrated DC-DC Converters for Modern Power Delivery Architectures
Song, Suyang; Novello, Alessandro; Jang, Taekwang (2024)
IEEE Solid-State Circuits Letters
This letter presents recent design challenges of modern power delivery architectures and circuit techniques for them. Recent computational loads impose significant power output demands on DC-DC converters while ever-shrinking Internet of Things (IoT) systems demand DC-DC converters with small footprints. Consequently, fully integrated DC-DC converters are highly desirable in contemporary power delivery architectures thanks to their compact footprint, high power density, and fast output regulation. However, numerous challenges exist in fully integrating DC-DC converters, necessitating the investigation of various circuit topologies and complex regulation schemes to ensure proper operation and versatility.
64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique
Harel, Odem; Casarrubias, Emmanuel Nieto; Eggimann, Manuel; et al. (2022)
IEEE Solid-State Circuits Letters
Gain-cell-embedded DRAM (GC-eDRAM) is an attractive alternative to traditional 6T SRAM, as it offers higher density, lower leakage power, and two-ported functionality. However, its refresh requirement also results in power consumption and memory access limitations. In this letter, we present a GC-eDRAM architecture designed to overcome the refresh disadvantages using a novel technique for improving the availability of the memory. In addition, by using a read-before-write mechanism, half select is supported. The macro avoids the need for supply boosting by employing 3T-1C bitcells and also integrates a replica bit line for optimal access timing to improve performance and power consumption. A 64- kB GC-eDRAM macro was fabricated in a 65- nm process technology, providing a 40% area reduction compared to a 6T SRAM cell, while achieving a 99.99% bit yield with a 16 mu s retention time.
An 8b 1.0-to-1.25GS/s Time-Based ADC with Bipolar VTC and Sense Amplifier Latch Interpolated Gated Ring Oscillator TDC
Yonar, A. Serdar; Francese, Pier Andrea; Brändli, Matthias; et al. (2023)
IEEE Solid-State Circuits Letters
An 8-bit digital intensive time-based ADC implemented in 5nm CMOS is presented in this work. It proposes a bipolar ramp-based voltage-to-time converter (BVTC) to eliminate the reference voltage and to allow a wide input swing of 0.75Vpp,diff. A redundancy scheme for the input polarity decision taken for 1-bit voltage domain folding is introduced against wrong decisions which eliminates comparator calibration in analog domain and allows a more efficient design. Sense amplifier latch (SAL) interpolation technique is presented which reduces the power and area consumption when phase interpolating the time-to-digital converter (TDC) signals. The ADC reaches 1GS/s sampling rate with 0.7V supply and 1.25GS/s with 0.8V supply and achieves 16.6fJ/conv-step and 20.3fJ/conv-step Walden FoM respectively. The total active area is 313μm2.
A Triple-Mode Cellular IoT SoC Achieving −136.8-dBm eMTC Sensitivity
Lippuner, Stefan; Salomon, Mauro; Korb, Matthias; et al. (2020)
IEEE Solid-State Circuits Letters
A triple-mode RF system on a chip (SoC) is reported which supports cellular Internet of Things (IoT) standards eMTC, NB-IoT, and EC-GSM, as well as 2G fallback. In the eMTC mode, the SoC achieves best-in-class performance for reference sensitivity (−112.3 dBm), coverage extension mode A (−128.5 dBm) and B (−136.8 dBm), respectively. A very efficient RTC, combined with dynamic power management of unused clocks and idle blocks, also leads to excellent performance in cellular IoT power-saving modes, such as extended discontinuous reception and power-saving mode.
A Buffer-Less Wideband Frequency Doubler in 45-nm CMOS-SOI with Transistor Multiport Waveform Shaping Achieving 25% Drain Efficiency and 46-89 GHz Instantaneous Bandwidth
Li, Sensen; Chi, Taiyun; Huang, Tzu-Yuan; et al. (2019)
IEEE Solid-State Circuits Letters
A wideband high-efficiency frequency doubler leveraging transistor multiport waveform shaping is presented in this letter. Unlike the conventional push-push pair with grounded source terminals, both the gates and sources of the proposed doubler are simultaneously driven by 180° out-of-phase signals. As a result, the drain current bifurcation is greatly reduced, leading to suppression of the undesired 4th harmonic and significant enhancement of 2nd harmonic current. The EKV FET model is also adopted to mathematically analyze the current waveform shaping in both conventional and proposed topologies, which agrees well with the circuit simulations. Broadband fundamental matching and a dual-resonance 2nd harmonic trap filter together guarantee the wideband frequency doubling performance. Prototyped in 45-nm CMOS-silicon-on-insulator, the proposed doubler achieves 25% peak drain efficiency, instantaneously covering 46-89 GHz (64% fractional bandwidth).
A Compact and PVT-Robust Segmented Duty-Cycled Resistor Realizing TΩ Impedances for Neural Recording Interface Circuits
Livanelioglu, Can; Choi, Woojun; Kim, Donghwan; et al. (2023)
IEEE Solid-State Circuits Letters
This letter presents an area-efficient and PVT-insensitive segmented duty-cycled resistor (SDR) intended for neural recording amplifiers. The feedback resistor of the capacitively-coupled low noise amplifier is realized with segmentation of the polysilicon resistor and supplementary switches in between. The proposed SDR suppresses impedance reduction due to switching of the resistor’s parasitic capacitance. It ensures higher than 1 TΩ resistance and a switching frequency above the signal bandwidth simultaneously, thus removing in-band switching artifacts and output DC drift. Fabricated in 0.18-μm CMOS, the prototype SDR achieves up to 1.18 TΩ with the smallest temperature variation of 6.5 % and chip-to-chip variation of 1.5 %, while only occupying an area of 0.001375 mm. Furthermore, it offers sufficiently low and stable cut-off frequencies for both action and local field potential recordings.
A Coarse-Fine VCO-ADC for MEMS Microphones with Sampling Synchronization by Data Scrambling
Quintero, Andres; Buffa, Cesare; Pérez, Carlos; et al. (2020)
IEEE Solid-State Circuits Letters
A 1.5GHz Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators and Resonant LC Flying Impedance achieving 4.1W/mm2 Peak Power Density and 77% Peak Efficiency
Novello, Alessandro; Atzeni, Gabriele; Keller, Tim; et al. (2024)
IEEE Solid-State Circuits Letters
This letter introduces a fully integrated DC-DC converter based on electromagnetically coupled class-D LC oscillators (EMLC) manufactured in a 22nm FDSOI CMOS process. The proposed converter implements a resonant LC flying impedance that improves the EMLC output resistance by accomplishing a resonant charge transfer between the flying capacitor CFLY and the load capacitor CO. This design achieves 77% peak efficiency and 4.1W/mm2 peak power density in a total area of 0.33mm2. The output voltage is regulated with a duty cycling scheme from 0.003W/mm2 up to 2.1W/mm2 with <2% efficiency loss.
A Noise-Efficient Neural Recording Amplifier Using Discrete-Time Parametric Amplification
Jang, Taekwang; Lim, Jongyup; Choo, Kyojin; et al. (2018)
IEEE Solid-State Circuits Letters

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Journal: IEEE Solid-State Circuits Letters

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