Journal: Digest of Technical Papers / IEEE International Solid State Circuits Conference

Abbreviation

Dig. tech. pap.- IEEE Int. Solid-State Circuits Conf.

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IEEE

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0193-6530
2376-8606

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Publications 1 - 10 of 48
  • 17.3 A 1.25GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators
    Item type: Conference Paper
    Novello, Alessandro; Atzeni, Gabriele; Cristiano, Giorgio; et al. (2021)
    Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2021 IEEE International Solid- State Circuits Conference (ISSCC)
    Over the past years, the constant reduction in the size of consumer electronics has strengthened the demand for fully integrated power management circuits. Buck converters offer high efficiency, but they cannot satisfy the stringent size requirements because bulky off-chip inductors are required [1]. Switched-capacitor (SC) approaches provide fully integrated power management solutions; however, their power density is limited by the on-chip capacitance density [2]. Resonant switched capacitor (ReSC) converters need 3D die-stacked inductors or PCB-integrated inductors to achieve appropriate power density values, posing challenges for monolithic integration [3]. A fully integrated ReSC has been presented [4], which implements an on-chip resonator, avoiding any external or 3D stacked passive components. However, the switching losses associated with the four transistors driving the resonator limit the switching frequency to 10s of MHz, bounding the power density scaling to 0.097W/mm 2.© 2021 IEEE.
  • A Quad-Band Class-39 RF CMOS Receiver for Evolved EDGE
    Item type: Conference Paper
    Dellsperger, Thomas; Tschopp, David; Rogin, Jürgen; et al. (2010)
    Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2010 IEEE International Solid-State Circuits Conference (ISSCC)
    A single-chip RF receiver to support EDGE Evolution with downlink dual-carrier (DLDC) receive diversity and EVM < 3% in all bands for demodulating 32-QAM signals is described. DLDC multistat class 39 and single-carrier multistat class 44 have been achieved. Both receive paths achieve a l\IF < 2.5 dB, an IIP3 >-3.5 dBm in the GSM 850/900 MHz band, and each draws < 57 mA from battery.
  • A single-chip CMOS micro-hotplate array for hazardous-gas detection and material characterization
    Item type: Conference Paper
    Barrettino, Diego; Graf, Markus; Hafizović, Sadik; et al. (2004)
    Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2004 IEEE International Solid-State Circuits Conference
    A single-chip microsystem for the detection and discrimination of hazardous gases and solid-state material characterization is presented. The circuit features three micro-hotplates, and each requires mixed-signal circuitry. The microsystem is fabricated in industrial 0.8/spl mu/m CMOS technology with post-CMOS micromachining. The power efficiency of the micro-hotplate is 10/spl deg/C/mW and represents a 60% improvement.
  • ReckOn: A 28nm Sub-mm2 Task-Agnostic Spiking Recurrent Neural Network Processor Enabling On-Chip Learning over Second-Long Timescales
    Item type: Conference Paper
    Frenkel, Charlotte; Indiveri, Giacomo (2022)
    Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2022 IEEE International Solid- State Circuits Conference (ISSCC)
    The robustness of autonomous inference-only devices deployed in the real world is limited by data distribution changes induced by different users, environments, and task requirements. This challenge calls for the development of edge devices with an always-on adaptation to their target ecosystems. However, the memory requirements of conventional neural-network training algorithms scale with the temporal depth of the data being processed, which is not compatible with the constrained power and area budgets at the edge. For this reason, previous works demonstrating end-to-end on-chip learning without external memory were restricted to the processing of static data such as images [1]–[4], or to instantaneous decisions involving no memory of the past, e.g. obstacle avoidance in mobile robots [5]. The ability to learn short-to-long-term temporal dependencies on-chip is a missing enabler for robust autonomous edge devices in applications such as gesture recognition, speech processing, and cognitive robotics.
  • A Linear Uplink WCDMA Modulator with 156dBc/Hz Downlink SNR
    Item type: Other Conference Item
    Papadopoulos, Dimitris; Huang, Qiuting (2007)
    Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)
    A linearity-boosting technique for upconversion mixers enables a 0.13 μm CMOS WCDMA modulator to achieve -49dBc ACLR and -l56dBc/Hz SNR. The chip consumes 113mW from a 1.2V supply. It is suitable for SAW-filter-free TX implementations. Results show that this technique improves the mixer IIP3 by 6dB.
  • A 24dBm 2-to-4.3GHz wideband digital Power Amplifier with built-in AM-PM distortion self-compensation
    Item type: Other Conference Item
    Park, Jongseok; Wang, Yanjie; Pellerano, Stefano; et al. (2017)
    Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2017 IEEE International Solid-State Circuits Conference (ISSCC)
    Modern wireless systems often support multi-standards with spectrum-efficient modulation schemes such as 64QAM and 256QAM and high data-rates. This poses stringent requirements on RF Power Amplifiers (PAs) for their carrier bandwidth, linearity, modulation rate, and efficiency. Several multiband Analog PAs (APAs) and Digital PAs (DPAs) are recently reported. However, multiband APAs often suffer from low power efficiency [1]. Although current-mode DPAs achieve high efficiency, high output power (P out ), and compact designs [2], they typically exhibit excessive AM-PM distortions intrinsically due to the digital power cell operations. Thus, current-mode DPAs often need frequency-dependent AM-PM look-up-tables for pre-distortion and/or real-time phase cancellation, resulting in additional overhead and difficult implementation for high modulation rates [3,4].
  • Multi-Functional Microelectrode Array System featuring 59’760 Electrodes, 2048 Electrophysiology Channels, Impedance and Neurotransmitter Measurement Units
    Item type: Other Conference Item
    Viswam, Vijay; Dragas, Jelena; Shadmani, Amir; et al. (2016)
    Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2016 IEEE International Solid-State Circuits Conference (ISSCC)
    Various CMOS-based micro-electrode arrays (MEAs) have been developed in recent years for extracellular electrophysiological recording/stimulation of electrogenic cells [1–5]. Mostly two approaches have been used: (i) the active-pixel approach (APS) [2–4], which features simultaneous readout of all electrodes, however, at the expense of a comparably high noise level, and (ii) the switch-matrix (SM) approach, which yields better noise performance, whereas only a subset of electrodes (e.g.,1024) is simultaneously read out [5]. All systems feature, at most, voltage recording and/or voltage/current stimulation functionalities.
  • 32.9 An Ultra-Compact 28GHz Doherty Power Amplifier with an Asymmetrically-Coupled-Transformer Output Combiner
    Item type: Conference Paper
    Liu, Edward; Wang, Hua (2024)
    Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2024 IEEE International Solid-State Circuits Conference (ISSCC)
    Mm-wave wireless communication and sensing heavily rely on phased arrays to compensate for high path losses and meet link-budget targets. Recent mm-wave arrays have grown increasingly complex, often with many parallel RF paths integrated on a single front-end/beamformer chip [1]. Dual-polarization and multiband operation further multiply the number of RF front-end paths. Consequently, one technology trend of array front-end chips is to aggressively miniaturize RF building blocks for integration and cost saving, while simultaneously achieving higher energy efficiency to maintain the thermal density and ease the packaging.
  • An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with 2× Interpolating Sense-Amplifier-Latches
    Item type: Conference Paper
    Yonar, Abdullah Serdar; Francese, Pier Andrea; Brändli, Matthias; et al. (2023)
    Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2023 IEEE International Solid- State Circuits Conference (ISSCC)
    Circuit innovations in medium-low resolution ADCs are among the key enablers to achieving higher data rates, currently at 224Gb/s [1], in the next-generation data-communication links based on sophisticated DSP techniques. The ADC interleaving factor is defined by the spectral efficiency of the signaling format and the maximum DSP clock rate. At every new generation, the DSP size shrinks thanks to CMOS scaling. However, DSP clock rates are not increasing with new technology nodes. In the 5nm CMOS technology used, the power performance area (PPA) sweet spot for the DSP resides within 0.7-0.8V supply and 1-2GHz clock frequency range. Circuit innovations are necessary for the ADC to benefit from scaling as much as the DSP. The sub-ADC architecture should be highly digital, amenable to automatic layout synthesis and operate in the same sweet spot. In addition, with the sub-ADC clock rate and supply matching the DSP, latency is reduced, and level shifting is avoided. For the modern modulation formats 7-8b resolution is adequate. Time-based ADCs are promising architectures thanks to their highly digital implementation, replacing analog building blocks with digital counterparts.
  • A current-mode wireless power receiver with optimal resonant cycle tracking for implantable systems
    Item type: Other Conference Item
    Choi, Myungjoon; Jang, Taekwang; Jeong, Junwon; et al. (2016)
    Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2016 IEEE International Solid-State Circuits Conference (ISSCC)
    Continuous health monitoring has become feasible, largely due to miniature implantable sensor systems such as [1]. To recharge batteries of such systems, wireless power transfer is a popular option since it is non-invasive. However, there are two main challenges: 1) strict safety regulations of incident power on human tissue; 2) small coil size for better biocompatibility. These issues reduce the received power at the coil, make it difficult to obtain sufficient power for implanted devices, and call for high power-efficiency (ηP)-transfer techniques, especially at very low received power levels.
Publications 1 - 10 of 48