Journal: IEEE Journal of Emerging and Selected Topics in Power Electronics

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IEEE

Journal Volumes

ISSN

2168-6777
2168-6785

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Publications 1 - 10 of 31
  • Miric, Spasoje; Giuffrida, Rosario V.; Bortis, Dominik; et al. (2020)
    IEEE Journal of Emerging and Selected Topics in Power Electronics
  • Tayyebi, Ali; Groß, Dominic; Anta, Adolfo; et al. (2020)
    IEEE Journal of Emerging and Selected Topics in Power Electronics
  • Leibl, Michael; Ortiz, Gabriel; Kolar, Johann W. (2017)
    IEEE Journal of Emerging and Selected Topics in Power Electronics
  • Zhang, Daifei; Cittanti, Davide; Sun, Pengpeng; et al. (2023)
    IEEE Journal of Emerging and Selected Topics in Power Electronics
    The three-phase (3- Φ) three-level (3-L) sparse neutral point clamped converter (SNPCC) combines a 3-L matrix stage and a 3- Φtwo-level (2-L) inverter stage to generate 3-L switched output voltages with a reduced transistor count (10 instead of 12 or 18) compared with the classical 3-L NPCC or 3-L active NPCC structure, targeting variable-speed drive (VSD) systems with low ripple of the motor phase currents or bidirectional 3- Φ power factor correcting (PFC) rectifier systems with reduced boost inductor volume. This article analyzes and experimentally characterizes the performance of an IGBT-based 3- Φ 3-L SNPCC and describes, for the first time, a hybrid current commutation effect between inverter-stage diodes and matrix-stage IGBTs that occurs when operating with lower modulation indices and leads to increased switching losses (up to 20% ). The proposed new semiconductor loss modeling approach accounts for this effect successfully, which is verified ( < 10% error) on an 800- Vdc, 7.5-kW SNPCC hardware demonstrator using a new in-situ calorimetric method that facilitates accurate stage-level semiconductor loss measurements. Heat spreading effects caused by the asymmetrical losses injection and thermal decoupling between two in-situ loss measurement blocks are carefully checked with finite-element method (FEM) simulations. Furthermore, an experimental evaluation of common-mode (CM) and differential-mode (DM) high-frequency (HF) voltage-time area ripples (as a generic measure for the required filtering effort) for three typical symmetrical and asymmetrical modulation switching state sequences is provided together with the semiconductor loss characterization. Utilizing a low-switching-loss asymmetric modulation scheme that operates the 3-L matrix stage and the 2-L inverter stage with the effective switching frequencies of 16 kHz and 5.3 kHz, respectively, the 3-L SNPCC demonstrator finally achieves a high rated power (7.5 kW, load current phase shift φ = 0 ) semiconductor efficiency of 98.8%.
  • Zhang, Daifei; Leontaris, Christos; Huber, Jonas; et al. (2024)
    IEEE Journal of Emerging and Selected Topics in Power Electronics
    Universal high-power three-phase (3-8) mains interfaces for electric vehicle (EV) charging must provide a wide output voltage range (e.g., 200–800 V) and, thus, provide buck and boost capability. An advantageous realization combining a three-level (3-L) T-type (Vienna) boost-type power-factor-correcting (PFC) voltage source rectifier (VSR) with a 3-L buck-type DC/DC converter stage is presented in this article. For high output voltages (boost mode), the VSR-stage operates with 3/3-pulsewidth modulation (PWM), i.e., continuous PWM of all three phases to regulate the output voltage, while the DC/DC-stage remains clamped to avoid switching losses. For low output voltages (buck mode), the DC/DC-stage advantageously controls the DC-link voltage according to a time-varying reference value, which allows to sinusoidally shape the currents of two mains phases, such that the VSR-stage can operate with 1/3-PWM (only one of the three bridge legs operates with PWM at any given time) with reduced switching losses. This article proposes a novel 2/3-PWM scheme for the output voltage transition region, where output voltages are between the buck mode and the boost mode. This enables loss-optimum operation (i.e., the minimum number of the VSR-stage bridge legs operating with PWM, and with the minimum possible DC-link voltage) for any output voltage. Furthermore, this article introduces a new synergetic control concept that ensures seamless transitions between the loss-optimum operating modes. A comprehensive experimental verification, including precompliance EMI measurements, using a 10-kW hardware demonstrator with a power density of 5.4 kW/dm3 (91 W/in3), a peak efficiency of 98.8% at rated power and 560-V output voltage, and >98% efficiency for all operating points with >400-V output voltage and more than about 50% of rated power confirms the theoretical analyses.
  • Herzog, Rahel; Menzi, David; Leibl, Michael; et al. (2025)
    IEEE Journal of Emerging and Selected Topics in Power Electronics
    DC loads or sources like motor drives, batteries, and strings of photovoltaic (PV) panels with power levels up to the lower single-digit kilowatt range are typically connected to the single-phase mains using bidirectional ac-dc converters providing power factor correction (PFC) functionality. Often, a dc output voltage range spanning from values lower than to values greater than the grid voltage amplitude is required, and hence, the ac-dc converter must provide buck-boost capability. As an alternative to conventionally used two-stage systems, single-stage converters promise lower realization effort and, in particular, fewer active components like power transistors. This article, therefore, analyzes a new bidirectional single-stage single-phase ac-dc buck-boost converter with only three power transistors, whose topology is identified using a systematic approach that is briefly summarized. Advantageously, the new ac-dc converter's negative dc output terminal is connected to the mains neutral, i.e., there is no common-mode (CM) voltage at the dc output. The operating principle is explained in detail, and a new advanced modulation method is proposed, which reduces the switching losses by more than 33% and lowers the component stresses. A 3.3-kW proof-of-concept (non-optimized) demonstrator is developed, which connects to the single-phase European ac mains (230 V rms, line-to-neutral) and provides a wide dc output voltage range of 300-450 V. Both the conventional and the proposed advanced modulation method are experimentally verified, confirming an improvement of the peak efficiency from 95.9% to 96.7% (300 V dc output, 2.5 kW output power) for the advanced modulation method.
  • Guillod, Thomas; Färber, Raphael; Rothmund, Daniel; et al. (2020)
    IEEE Journal of Emerging and Selected Topics in Power Electronics
    Newly available Medium-Voltage (MV) Silicon-Carbide (SiC) transistors are setting new limits for the design space of MV converters. Unprecedented blocking voltages, higher switching frequencies, higher commutation speeds, lower losses, and high temperature operation can be reached, which, however, create new challenges for the electrical insulation. In particular, the dielectric losses can become significant for MV converters operated at higher switching frequencies. Moreover, the evaluation of the dielectric losses is a key element for assessing the insulation stress and for insulation diagnostics. Therefore, this paper analyzes the modeling and the computation of dielectric losses with PWM voltages. After a review of the dielectric loss mechanisms occurring in polymeric insulation materials, scalable analytical expressions are proposed for the losses produced by PWM voltages. Afterwards, the dielectric losses of a Medium-Frequency (MF) transformer, employed in a 25 kW MV DC-DC converter (7 kV to 400 V) operated at 48 kHz, are analyzed and measured in detail. With epoxy resin, the insulation losses represent a significant share, i.e. up to 17 %, of the total transformer losses. As shown, the transformer performance can be significantly improved with a silicone elastomer insulation. Finally, design guidelines are provided for the selection of insulation materials.
  • Neumayr, Dominik; Knabben, Gustavo Carlos; Varescon, Elise; et al. (2021)
    IEEE Journal of Emerging and Selected Topics in Power Electronics
    One of the key technical challenges of the Google and IEEE Little Box competition, an international contest to build the world's smallest 2-kW single-phase inverter in 2015, was to shrink the volume of the energy storage required to cope with the twice mains-frequency (120 Hz) pulsating power at the ac side and meet the stringent 2.5% input voltage ripple at the dc side. In this article, first, a full-power processing buck-type converter active buffer approach, selected by the first prize winner of the Little Box Challenge (LBC), is analyzed in detail. Being relieved from strict voltage ripple requirements, a larger voltage ripple is allowed across the buffer capacitor significantly reducing the capacitance requirement. Second, a partial-power active buffer approach, selected by the second prize winner of the LBC, where conventional passive capacitive buffering of the dc-link is combined with a series-connected auxiliary converter, used to compensate for the remaining 120-Hz voltage ripple across the dc-link capacitance, is studied in detail. In this article, both the selected concepts are comparatively evaluated in terms of achievable efficiency, power density, and ripple compensation performance under both stationary and transient conditions. Novel control schemes and optimally designed hardware prototypes for both considered buffer concepts are presented and accompanied by experimental measurements to support the claimed efficiency and power density and assess the performance of the implemented control systems. Finally, by means of comparison with conventional passive dc-link buffering using only electrolytic capacitors, it is determined at what voltage ripple requirement it actually becomes beneficial in terms of volume to employ the considered active buffer concepts.
  • Antivachis, Michael; Wu, Dan; Bortis, Dominik; et al. (2022)
    IEEE Journal of Emerging and Selected Topics in Power Electronics
    The double-bridge voltage source inverter (DB-VSI) is a promising inverter topology for high performing motor drives. A DB-VSI comprises two VSIs, connected to the opposite sides of an open-end winding motor (no floating neutral point). Due to its inherent properties, a DB-VSI requires only half dc supply voltage, compared with a simple VSI, in order to generate the same motor voltage. Thereafter, by processing/switching only half of the dc supply voltage, the DB-VSI benefits from significantly lower semiconductor devices' switching losses. The DB-VSI technology is the main focus of this article. Namely, two different DB-VSI variants and/or modulation strategies are comparatively evaluated. After detailing the operating principle of each modulation strategy, the stresses on the inverter components are analytically derived. It is shown that the selection of the DB-VSI modulation strategy impacts the efficiency/power density of the inverter and the voltage quality of the motor. The theoretical considerations are subsequently verified within the context of a high-speed motor drive. In the investigated drive system, a fuel-cell supplies the inverter, which in return controls a 280-kr/min 1-kW electric compressor. Two DB-VSI hardware prototypes are purposely assembled and compared against a third state-of-the-art hardware prototype of the same specifications. It is shown that due to the DB-VSI technology, it is possible to reduce simultaneously the volume and the losses by up to 50% compared with the state-of-the-art solution. The low DB-VSI volume enables a seamless integration of the inverter in the motor housing. Accordingly, the open-end winding motor is directly attached to the inverter, eliminating the need for cumbersome and costly interconnecting cables. A final, integrated (inverter/motor) hardware prototype is presented, which further highlights the advantages of DB-VSI technology.
  • Boillat, David Olivier; Friedli, Thomas; Kolar, Johann W. (2017)
    IEEE Journal of Emerging and Selected Topics in Power Electronics
Publications 1 - 10 of 31