Journal: IEEE Journal of Solid-State Circuits

Abbreviation

IEEE J. Solid-State Circuits

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IEEE

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ISSN

0018-9200
1558-173X

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Publications1 - 10 of 125
  • A 141-dB dynamic range CMOS gas-sensor interface circuit without calibration with 16-bit digital output word
    Item type: Other Journal Item
    Grassi, Marco; Malcovati, Piero; Baschirotto, Andrea (2007)
    IEEE Journal of Solid-State Circuits
  • A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET
    Item type: Journal Article
    Jaewon, Lee; Francese, Pier-Andrea; Bräendli, Matthias; et al. (2025)
    IEEE Journal of Solid-State Circuits
    This article presents a 112-Gb/s discrete multitone (DMT) wireline receiver (RX) datapath with a 50-GS/s, 8-bit, 64-way ( 8×8 ) time-interleaved time-based analog-to-digital converter (TI-TBADC) in a 5-nm FinFET. The TBADC converts the voltage input into a time-domain quantity using a ring oscillator (ROSC). Eight-slice TBADCs, driven from the same first-rank interleaver, share the identical injection-locked ROSC (IROSC) for voltage-to-time conversion (VTC). The DMT digital signal processor (DSP) achieves optimal bit and power loading with 63 orthogonal subchannels by employing a 64-way single-stage multi-path delay feedback (MDF) fast Fourier transform (FFT) core. An on-chip sign-sign least mean square (SS-LMS) engine adapts equalizer coefficients to combat channel fluctuation. The RX prototype demonstrates 4E-4 BER when communicating over the channel, exhibiting 18-dB insertion loss (IL) at Nyquist, while consuming 347-mW power and 0.242-mm2 silicon area.
  • ASIC Implementation of Soft-Input Soft-Output MIMO Detection Using MMSE Parallel Interference Cancellation
    Item type: Journal Article
    Studer, Christoph; Fateh, Schekeb; Seethaler, Dominik (2011)
    IEEE Journal of Solid-State Circuits
  • A Broadband Linear Ultra-Compact mm-Wave Power Amplifier with Distributed-Balun Output Network: Analysis and Design
    Item type: Journal Article
    Wang, Fei; Wang, Hua (2021)
    IEEE Journal of Solid-State Circuits
    This article presents a broadband power amplifier (PA) with a distributed-balun output network that provides the PA optimum load impedance over a wide bandwidth. The proposed output network comprises two coupled-line sections and absorbs the device output capacitance. It employs a scalable coupled-line modeling approach that captures both the magnetic (inductive) and electric (capacitive) couplings between windings with fewer parameters and supports a rapid design process. Closed-form design solutions, design space limitations, bandwidth limits, and design tradeoffs are derived and analyzed comprehensively. Its extension to differential output and common-mode response is also discussed in detail. As a proof of concept, a prototype PA is implemented for multiband fifth-generation (5G) applications in 45-nm SOI CMOS. With no biasing retuning or network reconfiguration, the PA consistently achieves >19.1 dBm $P_{\mathrm {sat}}$ , >37.3% peak power-added efficiency (PAE), 17.8-19.6 dBm $P_{\mathrm {1dB}}$ , and 36.6%-44.3% PAE $_{P\mathrm {1dB}}$ over 24-40 GHz, verifying the truly wideband large-signal matching. The PA demonstrates 5G new radio (NR) frequency range 2 (FR2) modulation signals over 24-42 GHz, covering n257/n258/n260 5G bands. For 5G NR FR2 800-MHz 2-CC 64-QAM signals (11.78-dB PAPR), the PA achieves 11.3-dBm/16.6% average $P_{\mathrm {out}}$ /PAE with -25.1-dB rms EVM at 28-GHz and 10.2-dBm/13.6% average $P_{\mathrm {out}}$ /PAE with -25.1-dB rms EVM at 37 GHz.
  • A Low-Power Baseband ASIC for an Energy-Collection IR-UWB Receiver
    Item type: Journal Article
    Barras, David; Meyer-Piening, Robert; Bueren, George von; et al. (2009)
    IEEE Journal of Solid-State Circuits
  • How to Keep Pushing ML Accelerator Performance? Know Your Rooflines!
    Item type: Journal Article
    Verhelst, Marian; Benini, Luca; Verma, Naveen (2025)
    IEEE Journal of Solid-State Circuits
    The rapidly growing importance of machine learning (ML) applications, coupled with their ever-increasing model size and inference energy footprint, has created a strong need for specialized ML hardware architectures. Numerous ML accelerators have been explored and implemented, primarily to increase task-level throughput per unit area and reduce task-level energy consumption. This article surveys key trends toward these objectives for more efficient ML accelerators and provides a unifying framework to understand how compute and memory technologies/architectures interact to enhance system-level efficiency and performance. To achieve this, this article introduces an enhanced version of the roofline model and applies it to ML accelerators as an effective tool for understanding where various execution regimes fall within roofline bounds and how to maximize performance and efficiency under the roofline. Key concepts are illustrated with examples from state-of-the-art (SOTA) designs, with a view toward open research opportunities to further advance accelerator performance.
  • An 8.62-μW 75-dB DR(SoC) Fully Integrated SoC for Spoken Language Understanding
    Item type: Journal Article
    Zhou, Sheng; Li, Zixiao; Cheng, Longbiao; et al. (2025)
    IEEE Journal of Solid-State Circuits
    We present a sub-10- μ W fully integrated SoC for on-device spoken language understanding (SLU). Its analog feature extractor (FEx) applies global and per-channel automatic gain control (AGC) to extend the system’s dynamic range (DR)—a critical requirement for real-world scenarios, including far-field operations. The on-chip streaming-mode recurrent neural network (RNN) accelerator exploits temporal sparsity and pooling, reducing its power by 2.3× . By combining hardware-aware training with a behavioral model of the FEx that captures circuit nonidealities, the network is trained to maintain SLU accuracy despite chip-to-chip variation. Fabricated in a 65-nm CMOS process, the SoC occupies 2.23 mm2 and consumes 8.62 μ W for end-to-end SLU. The 16-channel FEx achieves 93-dB DR while dissipating 1.85 μ W at 100-Hz feature frame rate. The SoC is evaluated on the 32-class Fluent Speech Commands dataset (FSCD), achieving 92.9% accuracy for 2.8-mVrms inputs while maintaining >85% accuracy over a 75-dB input range.
  • An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389 MΩ Input Impedance
    Item type: Journal Article
    Atzeni, Gabriele; Livanelioglu, Can; Arjmandpour, Sina; et al. (2024)
    IEEE Journal of Solid-State Circuits
    This article presents a transformer-first analog front-end (AFE) for ultra-low-power sensor nodes. The proposed AFE employs a discrete-time transformer based on series–parallel converters as an input stage. The switched-capacitor (SC) transformer can provide a passive low-noise voltage gain, attenuating the input-referred noise (IRN) of the following continuous-time chain. However, it also degrades the AFE input impedance. As a remedy, this article presents an input-resistance-boosting (IRB) loop that successfully increases the input resistance, sensing the output of a following continuous-time stage. At the same time, we also introduce an input-capacitance-canceling (ICC) loop to improve the input impedance at high frequencies. The proposed AFE achieves 389- MΩ input impedance at 1 kHz, which represents a 39 × improvement compared to prior work. Moreover, it attains superior noise efficiency, with an IRN of 1.36 μVrms , while consuming 370 nW. This results in a noise efficiency factor (NEF) of 0.34 and a power efficiency factor (PEF) of 0.1, the lowest reported values to the best of the authors’ knowledge. The impedance-boosted chain consisting of the SC transformer, first continuous-time amplifier (CTA), and the IRB loop achieves an NEF of 0.27 and a PEF of 0.06.
  • Multi-Feed Antenna and Electronics Co-Design: An E-Band Antenna-LNA Front End with On-Antenna Noise-Canceling and G-Boosting
    Item type: Journal Article
    Li, Sensen; Chi, Taiyun; Wang, Hua (2020)
    IEEE Journal of Solid-State Circuits
    This article presents an E-band low-noise amplifier (LNA) co-designed and co-integrated with an on-chip multifeed antenna for antenna-level LNA noise-canceling and gm -boosting. Different from conventional approaches that view antennas as a simple 50-Ω radiation load, we exploit antennas as multi-feed passive radiating networks with direct onantenna signal conditioning and processing capabilities. Such an antenna-electronics co-design concept can potentially advance wireless front-end performance beyond electronics-only designs and opens the door to a plethora of front-end innovations. We also propose equivalent circuits to model multi-feed antenna systems and elucidate on-antenna signal processing operations. As a proof of concept, we propose an antenna-LNA co-designed architecture and explore the interactions among a common-gate (CG) LNA path, a common-source (CS) LNA path, and a pair of near-field coupled folded slot antennas for on-antenna noise-cancellation and g m -boosting. In the measurements, a true V-factor radiation method is introduced as a new approach to measure the noise figure (NF) of the on-chip multi-feed antenna and LNA/RX integration. Then, we perform the conventional sensitivity-based NF measurement. Both measurements show accurate and consistent NF characterization at high millimeter-wave (mm-Wave). The E-band antenna-LNA front end is implemented in the Globalfoundries 45-nm CMOS SOI process and demonstrates 4.8-dB NF with 2.2-dBm IIP 3 , achieving the best reported FoM at similar frequencies. Furthermore, over-the-air modulation tests are demonstrated, supporting >10-Gb/s high-fidelity high-order QAM signals over an E-band wireless link.
  • A 40-Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45-nm SOI CMOS
    Item type: Journal Article
    Moazeni, Sajjad; Lin, Sen; Wade, Mark; et al. (2017)
    IEEE Journal of Solid-State Circuits
Publications1 - 10 of 125