Journal: IEEE Open Journal of the Solid-State Circuits Society

Abbreviation

Publisher

IEEE

Journal Volumes

ISSN

2644-1349

Description

Filters

2022 - 20263
Reset filters

Search Results

Publications1 - 3 of 3
  • A Digital Power Amplifier With Built-In AM–PM Compensation and a Single-Transformer Output Network
    Item type: Journal Article
    Lee, Jeongseok; Jung, Doohwan; Munzer, David; et al. (2023)
    IEEE Open Journal of the Solid-State Circuits Society
    This article presents a digital power amplifier (DPA) with a built-in AM–PM compensation technique and a compact single-transformer footprint. The AM–PM distortion behavior of the current-mode/voltage-mode power amplifiers (PAs) is detailed and an AM–PM compensation technique for both modes is introduced. The proposed design utilizes one current-mode DPA as the main path PA and a class-G PA voltage-mode digital PA as the auxiliary path PA, combined through a single-transformer footprint. It provides enhanced linearity through built-in adaptive biasing and hybrid current-/voltage-mode Doherty-based power combining. As a proof of concept, a 1.2–2.4-GHz wideband DPA is implemented in the Globalfoundries 45-nm CMOS SOI process. The measurements show a 37.6% peak drain efficiency (DE) at 1.4 GHz, and 21.8-dBm saturated output power (Psat) and 1.2×/1.4× power back-off (PBO) efficiency enhancement, compared to the ideal class-B at 3 dB/6 dB PBO at 1.2 GHz. This proposed digital PA supports 20-MSym/s 64-QAM modulation at 14.8-dBm average output power and 22.8% average PA DE while maintaining error vector magnitude (EVM) lower than −23 dB without any phase predistortion. To the best of our knowledge, this is the first demonstration of hybrid current–voltage-mode Doherty power combining on a single-footprint transformer over a broad bandwidth (BW).
  • DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training
    Item type: Journal Article
    Garofalo, Angelo; Tortorella, Yvan; Perotti, Matteo; et al. (2022)
    IEEE Open Journal of the Solid-State Circuits Society
    On-chip deep neural network (DNN) inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy, and flexibility requirements. Heterogeneous clusters are promising solutions to meet the challenge, combining the flexibility of DSP-enhanced cores with the performance and energy boost of dedicated accelerators. We present DARKSIDE, a System-on-Chip with a heterogeneous cluster of eight RISC-V cores enhanced with 2-b to 32-b mixed-precision integer arithmetic. To boost the performance and efficiency on key compute-intensive DNN kernels, the cluster is enriched with three digital accelerators: 1) a specialized engine for low-data-reuse depthwise convolution kernels (up to 30 MAC/cycle); 2) a minimal overhead datamover to marshal 1–32-b data on-the-fly; and 3) a 16-b floating-point tensor product engine (TPE) for tiled matrix-multiplication acceleration. DARKSIDE is implemented in 65-nm CMOS technology. The cluster achieves a peak integer performance of 65 GOPS and a peak efficiency of 835 GOPS/W when working on 2-b integer DNN kernels. When targeting floating-point tensor operations, the TPE provides up to 18.2 GFLOPS of performance or 300 GFLOPS/W of efficiency—enough to enable on-chip floating-point training at competitive speed coupled with ultralow power quantized inference.
  • Review on the Temperature Resilient On-Chip Frequency Generation Circuit Techniques
    Item type: Review Article
    Cho, Kyuik; Ansari, Elaheh; Jang, Taekwang (2026)
    IEEE Open Journal of the Solid-State Circuits Society
    This article summarizes temperature-resilient on-chip frequency generation circuit techniques, focusing on low-power and compact implementations suitable for miniaturized Internet of Things (IoT) systems. While various types of oscillators–such as MEMS, crystal, LC, RC, gate-leakage, and ring oscillators–are employed to generate reference frequencies, on-chip RC oscillators are particularly attractive due to their compatibility with standard CMOS processes and significant improvements in power consumption and frequency accuracy over the last decade. However, without consideration of temperature dependency, the frequency stability can be severely degraded, which limits their applicability in high-precision systems. To address this challenge, we investigate temperature-dependent non-idealities of the on-chip RC oscillators and introduce various on-chip RC oscillator architectures, including frequency-locked loop-based oscillators, and techniques to improve temperature dependency in the RC oscillators, such as current mismatch, comparator delay, and comparator input offset.
Publications1 - 3 of 3