Journal: IEEE Computer Architecture Letters

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IEEE

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1556-6064
2473-2575

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2017 - 201922020 - 20243
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Publications 1 - 5 of 5
  • A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM
    Item type: Journal Article
    Khan, Samira; Wilkerson, Chris; Lee, Donghyuk; et al. (2017)
    IEEE Computer Architecture Letters
  • NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories
    Item type: Journal Article
    Rezaei, S.H.S.; Modarressi, Mehdi; Ausavarungnirun, Rachata; et al. (2020)
    IEEE Computer Architecture Letters
  • Address Scaling: Architectural Support for Fine-Grained Thread-Safe Metadata Management
    Item type: Journal Article
    Mishra, Deepanjali; Kanellopoulos, Konstantinos; Panwar, Ashish; et al. (2024)
    IEEE Computer Architecture Letters
    In recent decades, software systems have grown significantly in size and complexity. As a result, such systems are more prone to bugs which can cause performance and correctness challenges. Using run-time monitoring tools is one approach to mitigate these challenges. However, these tools maintain metadata for every byte of application data they monitor, which precipitates performance overheads from additional metadata accesses. We propose Address Scaling, a new hardware framework that performs fine-grained metadata management to reduce metadata access overheads in run-time monitoring tools. Our mechanism is based on the observation that different run-time monitoring tools maintain metadata at varied granularities. Our key insight is to maintain the data and its corresponding metadata within the same cache line, to preserve locality. Address Scaling improves the performance of Memcheck, a dynamic monitoring tool that detects memory-related errors, by 3.55x and 6.58x for sequential and random memory access patterns respectively, compared to the state-of-the-art systems that store the metadata in a memory region that is separate from the data.
  • LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory
    Item type: Journal Article
    Boroumand, Amirali; Ghose, Saugata; Patel, Minesh; et al. (2017)
    IEEE Computer Architecture Letters
  • Ramulator 2: A Modern, Modular, and Extensible DRAM Simulator
    Item type: Journal Article
    Luo, Haocong; Tuğrul, Yahya Can; Bostancı, F. Nisa; et al. (2024)
    IEEE Computer Architecture Letters
    We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and DRAM to meet the increasing research effort in improving the performance, security, and reliability of memory systems. Ramulator 2.0 abstracts and models key components in a DRAM-based memory system and their interactions into shared interfaces and independent implementations. Doing so enables easy modification and extension of the modeled functions of the memory controller and DRAM in Ramulator 2.0. The DRAM specification syntax of Ramulator 2.0 is concise and human-readable, facilitating easy modifications and extensions. Ramulator 2.0 implements a library of reusable templated lambda functions to model the functionalities of DRAM commands to simplify the implementation of new DRAM standards, including DDR5, LPDDR5, HBM3, and GDDR6. We showcase Ramulator 2.0's modularity and extensibility by implementing and evaluating a wide variety of RowHammer mitigation techniques that require different memory controller design changes. These techniques are added modularly as separate implementations without changing any code in the baseline memory controller implementation. Ramulator 2.0 is rigorously validated and maintains a fast simulation speed compared to existing cycle-accurate DRAM simulators. Ramulator 2.0 is open-sourced under the permissive MIT license at https://github.com/CMU-SAFARI/ramulator2
Publications 1 - 5 of 5