Frank Kagan Gürkaynak
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Last Name
Gürkaynak
First Name
Frank Kagan
ORCID
Organisational unit
03996 - Benini, Luca / Benini, Luca
71 results
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Publications 1 - 10 of 71
- 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processingItem type: Conference Paper
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2016 (IEEE COOL CHIPS XIX)Rossi, Davide; Pullini, Antonio; Loi, Igor; et al. (2016) - Approximate 32-bit Floating-point Unit Design with 53% Power-area Product ReductionItem type: Conference Paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits ConferenceCamus, Vincent; Schlachter, Jeremy; Enz, Christian; et al. (2016) - Evaluation of the Back-End Design Overhead for ASIC Implementations of Large-Operand Multipliers Targeting Resource-Constrained EnvironmentsItem type: Conference Paper
22nd Austrian Workshop on Microelectronics (Austrochip). 9 October 2014, Graz, Austria. ProceedingsNagl, Christoph; Muehlberghuber, Michael; Gürkaynak, Frank Kagan (2014) - Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core ClustersItem type: Conference Paper
2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH)Schaffner, Michael; Gautschi, Michael; Gürkaynak, Frank Kagan; et al. (2016) - Near-Threshold RISC-V core with DSP extensions for scalable IoT endpoint devicesItem type: Journal Article
IEEE Transactions on Very Large Scale Integration (VLSI) SystemsGautschi, Michael; Schiavone, Pasquale D.; Traber, Andreas; et al. (2017) - MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warpingItem type: Conference Paper
2013 Proceedings of the European Solid-State Circuits Conference (ESSCIRC)Schaffner, Michael; Greisen, Pierre; Heinzle, Simon; et al. (2013)In this paper, a video rendering ASIC for multiview automultiscopic displays using an image domain warping approach is presented. The video rendering core is able to synthesize up to nine interleaved views from full-HD (1080p) stereoscopic 3D input footage. The design employs elliptical weighted average (EWA) splatting to perform the image resampling. We use the mathematical properties of the Gaussian filters of EWA splatting to analytically integrate display anti-aliasing into the resampling step. The use of realistic assumptions on the image transformation enable a hardware architecture that operates on a video stream in scan-line fashion and that does not require an off-chip memory. The ASIC, fabricated in a 65nm CMOS technology, runs at 260MHz and is able to deliver 28.7 interleaved full-HD (1080p) frames per second with eight views enabled. It has a core power dissipation of 550mW and its complexity is 6.8 MGE, including 4.36 MBit SRAM macros. - An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore ClusterItem type: Journal Article
IEEE Journal of Solid-State CircuitsGautschi, Michael; Schaffner, Michael; Gürkaynak, Frank Kagan; et al. (2017) - A real-time 720p feature extraction core based on Semantic Kernels BinarizedItem type: Conference Paper
Proceedings of 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)Schaffner, Michael; Hager, Pascal; Cavigelli, Lukas; et al. (2013) - Area, throughput and security considerations for AES Crypto-ASICsItem type: Conference Paper
2005 PhD research in microelectronics and electronics : PRIME ; proceedings of the conference ; Lausanne, Switzerland, July 25 - 28, 2005Gürkaynak, Frank Kagan; Felber, Norbert; Kaeslin, Hubert; et al. (2005) - Towards Evaluating High-Speed ASIC Implementations of CAESAR Candidates for Data at Rest and Data in MotionItem type: Other Conference ItemMuehlberghuber, Michael; Gürkaynak, Frank Kagan (2015)
Publications 1 - 10 of 71