Seyedhadi Mirfarshbafan


Last Name

Mirfarshbafan

First Name

Seyedhadi

ORCID

0000-0002-3400-2122

Organisational unit

09695 - Studer, Christoph / Studer, Christoph

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2019 - 201912020 - 202517
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Publications 1 - 10 of 18
  • A 46 Gbps 12 pJ/b Sparsity-Adaptive Beamspace Equalizer for mmWave Massive MIMO in 22FDX
    Item type: Journal Article
    Mirfarshbafan, Seyedhadi; Studer, Christoph (2024)
    IEEE Transactions on Circuits and Systems II. Express Briefs
    We present a GlobalFoundries 22FDX FD-SOI application-specific integrated circuit (ASIC) of a beamspace equalizer for millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) systems. The ASIC implements a recently-proposed power-saving technique called sparsity-adaptive equalization (SPADE). SPADE exploits the inherent sparsity of mmWave channels in the beamspace domain to reduce the dynamic power of matrix-vector products by skipping multiplications for which the magnitude of both operands are below pre-defined thresholds. Simulations with realistic mmWave channels show that SPADE incurs less than 0.7 dB SNR degradation at 1% target bit error rate compared to antenna-domain equalization. ASIC measurement results demonstrate an equalization throughput of 46 Gbps and show that SPADE offers up to 38% power savings compared to antenna-domain equalization. A comparison with state-of-the-art massive MIMO equalizer designs reveals that our ASIC achieves superior normalized energy efficiency.
  • Hardware-Aware Beamspace Precoding for All-Digital mmWave Massive MU-MIMO
    Item type: Journal Article
    Gönültaş, Emre; Taner, Sueda; Gallyas-Sanhueza, Alexandra; et al. (2021)
    IEEE Communications Letters
    Massive multi-user multiple-input multiple-output (MU-MIMO) wireless systems operating at millimeter-wave (mmWave) frequencies enable simultaneous wideband data transmission to a large number of users. In order to reduce the complexity of MU precoding in all-digital basestation architectures, we propose a two-stage precoding architecture that first performs precoding using a sparse matrix in the beamspace domain, followed by an inverse fast Fourier transform that converts the result to the antenna domain. The sparse precoding matrix requires a small number of multipliers and enables regular hardware architectures, which allows the design of hardware-efficient all-digital precoders. Simulation results demonstrate that our methods approach the error-rate of conventional Wiener filter precoding with more than 2\times reduced complexity.
  • Sparsity-adaptive equalization for communication systems
    Item type: Patent
    Mirfarshbafan, Seyedhadi; Studer, Christoph (2024)
    A wireless communication system can include an antenna and an equalization system. The antenna can be configured to wirelessly receive a data signal from a user equipment (UE). The equalization system can be configured to compensate for distortion incurred by the data signal during propagation. The equalization system can include a set of multiplier circuits. Each multiplier circuit can include a first input, a second input, a multiplier device, and a management circuit. The first input can receive a first input signal that corresponds to the data signal. The second input can receive a second input signal that corresponds to a weighting value assigned to a channel associated with the antenna. The multiplier device can be enabled or disabled. When enabled, the multiplier device can be configured to perform a multiplication operation on the first input signal and the second input signal. When disabled, the multiplier circuit may not perform the multiplication operation. The management circuit can be configured to selectively disable or enable the multiplier device based on the first input signal and/or the second input signal, thereby reducing an effective number of multiplications and offering power savings.
  • SPADE: Sparsity-Adaptive Equalization for MMwave Massive MU-MIMO
    Item type: Conference Paper
    Mirfarshbafan, Seyedhadi; Studer, Christoph (2021)
    2021 IEEE Statistical Signal Processing Workshop (SSP)
    We propose SParsity-ADaptive Equalization (SPADE), a novel approach to reduce the effective number of multiplications in sparse inner products by adaptively skipping multiplications that have little to no effect on the result. We apply SPADE to beamspace linear minimum mean square error (LMMSE) spatial equalization in all-digital millimeter-wave (mmWave) massive multiuser multiple-input multiple-output (MU-MIMO) systems. We propose a SPADE-based architecture that mutes insignificant multiplications to offer power savings. We use simulation results with line-of-sight (LoS) and non-LoS mmWave channel models to demonstrate that SPADE-LMMSE performs on par with state-of-the-art beamspace equalizers in terms of bit error-rate, while requiring significantly lower preprocessing complexity.
  • BEACHES: Beamspace Channel Estimation for Multi-Antenna mmWave Systems and Beyond
    Item type: Conference Paper
    Ghods, Ramina; Gallyas-Sanhueza, Alexandra; Mirfarshbafan, Seyedhadi; et al. (2019)
    2019 IEEE 20th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC)
  • A Resolution-Adaptive 8 mm2 9.98 Gb/s 39.7 pJ/b 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS
    Item type: Conference Paper
    Castañeda Fernández, Oscar; Boynton, Zachariah; Mirfarshbafan, Seyedhadi; et al. (2021)
    ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
    All-digital millimeter-wave (mmWave) massive multi-user multiple-input multiple-output (MU-MIMO) receivers enable extreme data rates but require high power consumption. In order to reduce power consumption, this paper presents the first resolution-adaptive all-digital receiver ASIC that is able to adjust the resolution of the data-converters and baseband-processing engine to the instantaneous communication scenario. The scalable 32-antenna, 65 nm CMOS receiver occupies a total area of 8 mm^2 and integrates analog-to-digital converters (ADCs) with programmable gain and resolution, beamspace channel estimation, and a resolution-adaptive processing-in-memory spatial equalizer. With 6-bit ADC samples and a 4-bit spatial equalizer, our ASIC achieves a throughput of 9.98 Gb/s while being at least 2x more energy-efficient than state-of-the-art designs.
  • Sparsity-Adaptive Beamspace Channel Estimation for 1-Bit mmWave Massive MIMO Systems
    Item type: Conference Paper
    Gallyas-Sanhueza, Alexandra; Mirfarshbafan, Seyedhadi; Ghods, Ramina; et al. (2020)
    2020 IEEE 21st International Workshop on Signal Processing Advances in Wireless Communications (SPAWC)
  • Beamspace Channel Estimation for Massive MIMO mmWave Systems: Algorithm and VLSI Design
    Item type: Journal Article
    Mirfarshbafan, Seyedhadi; Gallyas-Sanhueza, Alexandra; Ghods, Ramina; et al. (2020)
    IEEE Transactions on Circuits and Systems I: Regular Papers
  • Sparse Beamspace Equalization for Massive MU-MIMO MMWave Systems
    Item type: Conference Paper
    Mirfarshbafan, Seyedhadi; Studer, Christoph (2020)
    ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
  • Algorithm and VLSI Design for 1-bit Data Detection in Massive MIMO-OFDM
    Item type: Journal Article
    Mirfarshbafan, Seyedhadi; Shabany, Mahdi; Nezamalhosseini, S. Alireza; et al. (2020)
    IEEE Open Journal of Circuits and Systems
    The use of low-resolution data converters in the radio-frequency (RF) chains of all-digital massive multiple-input multiple-output (MIMO) basestations promises significant reductions in power consumption, hardware costs, and interconnect bandwidth. We propose a quantization-aware data detection algorithm which mitigates the performance loss of 1-bit quantized massive MIMO orthogonal frequency-division multiplexing (OFDM) systems. Since the system performance heavily depends on the quality of channel estimates, we also develop a nonlinear 1-bit channel estimation algorithm that builds upon the proposed data detection algorithm. We show that the proposed algorithms significantly outperform linear data detectors and channel estimators in terms of bit error rate. For the proposed nonlinear data detection algorithm, we develop a very large scale integration (VLSI) architecture and present implementation results on a Xilinx Virtex-7 field programmable gate array (FPGA). Our implementation results are, to the best of our knowledge, the first for 1-bit massive MU-MIMO-OFDM systems and demonstrate comparable hardware efficiency with respect to state-of-the-art linear data detectors designed for systems with high-resolution data converters, while achieving lower bit error rate.
Publications 1 - 10 of 18