Diego Calvo Ruiz


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Calvo Ruiz

First Name

Diego

ORCID

0000-0001-6170-6427

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Publications 1 - 8 of 8
  • InAs Channel Inset Effects on the DC, RF, and Noise Properties of InP pHEMTs
    Item type: Journal Article
    Calvo Ruiz, Diego; Saranovac, Tamara; Han, Daxin; et al. (2019)
    IEEE Transactions on Electron Devices
  • InP High Electron Mobility Transistors with InAs-based Channels for High Frequency and Low Noise Applications
    Item type: Doctoral Thesis
    Calvo Ruiz, Diego (2020)
    Indium phosphide based high electron mobility transistors (InP HEMTs) offer outstanding channel transport properties required for high-speed, high-gain and low-noise performance. They are the key components of low-noise receivers, and their field of application includes telecommunications, imaging, spectroscopy and even quantum computing. For years they have been considered as the best option for low-noise amplifiers, where the most critical metrics depend not only on speed and gain but also on noise performance both at room and cryogenic temperatures. Although gate length miniaturization and channel composition optimization enable record cutoff frequencies, noise performance shows a different trend. Further developments in noise of sub-100 nm devices are not achieved due to their increased drain noise. Additionally, vertical device scaling entails higher gate leakage, thus degrading the noise performance even further. This work covers the epitaxial layer optimization of InP HEMTs with InAs channel insets using bandgap engineering and varying the device geometry. Composite channel structures with narrow and wide bandgap materials were implemented to reduce the effects of impact ionization and lower the gate leakage currents while keeping an excellent RF performance. Devices were characterized by extensive DC and RF measurements at room and cryogenic temperatures. To correlate the device results to its circuit behavior, small-signal device modeling was performed for various epitaxial structures. The used small-signal model accounts for the effects of impact ionization and presents excellent agreement between measured and simulated data. Noise performance at room temperature was also investigated by means of noise parameters measurements. Based on the figures-of-merits for different device geometries and layer stacks, further developments in the fabrication technology could be identified, leading to progress in noise performance.
  • Gate Recess Etch Sensitivity of Thick and Highly-Doped GaInAs Cap Layer in InP HEMT Fabrication
    Item type: Conference Paper
    Han, Daxin; Calvo Ruiz, Diego; Saranovac, Tamara; et al. (2020)
    CS MANTECH 2020 Digest of Papers
    The use of highly-doped thick cap layers is a common strategy to enhance the performance of GaInAs/AlInAs/InP High Electron Mobility Transistors (HEMTs) by reducing the Ohmic contact resistance (RC). However, because of the high doping level, cap layers become very sensitive to processing steps performed before and during gate recess etching. In this paper, the sensitivity of gate recess etching on a 20 nm highly-doped GaInAs cap layer (doped 7.3 × 1019 cm-3) is studied with respect to Ohmic contact type (annealed/non-annealed), chip size, gate finger length, and etchant choice. The use of very high cap doping levels exacerbates device and process scaling challenges. For example, the recess finger length dependence complicates multi-project wafer runs which would simultaneously include narrow finger HEMTs used in digital ICs and longer finger HEMTs used in microwave analog circuits.
  • High-Speed Steep-Slope GaInAs Impact Ionization MOSFETs (I-MOS) With SS = 1.25 mV/dec - Part II: Dynamic Switching and RF Performance
    Item type: Journal Article
    Han, Daxin; Bonomo, Giorgio; Calvo Ruiz, Diego; et al. (2022)
    IEEE Transactions on Electron Devices
    Part I of this work described narrow bandgap GaInAs-based I-MOS devices with a minimum steep slope SSmin = 1.25 mV/dec maintained over 4 orders of magnitude in drain current, ION/IOFF ratios >106 at 300 K (>109 at 15 K), and low operating voltages for a gate length of LG = 100 nm. Part II focuses on the device time-domain switching capabilities and RF performance. Digital switching tests using a hybrid connected inverter reveal excellent capabilities for high clock rate operation. Simple circuit estimates indicate that the present 100 nm GaInAs I-MOS can operate with clock frequencies >10 GHz. The impact-ionization-induced hysteresis in the ID – VGS I-MOS characteristics does not play any role in dynamic switching of a digital inverter: the n -channel pull-down transistor turns on with a steep slope, but turns off classically with a higher threshold voltage which reduces the dynamic power dissipation per switching cycle. Factors impacting GaInAs I-MOS reliability are considered, and a physically motivated approach to enhance the reliability of III–V MOSFETs is proposed. We show that GaInAs-based I-MOS devices offer high analog cutoff frequencies and low-noise characteristics, suggesting applicability for digital and RF applications on a single technological platform. When benchmarked against other steep-slope technologies, GaInAs I-MOS shows the strongest steep slope, competitive ION/IOFF ratios, and lowest operating voltage of any I-MOS transistor to date, without any back-gate/substrate bias.
  • Low-Noise Microwave Performance of 30 nm GaInAs MOS-HEMTs: Comparison to Low-Noise HEMTs
    Item type: Journal Article
    Han, Daxin; Calvo Ruiz, Diego; Bonomo, Giorgio; et al. (2020)
    IEEE Electron Device Letters
    GaInAs-based Metal Oxide Semiconductor High Electron Mobility Transistors (MOS-HEMTs) can in principle combine the wide bandwidth of HEMTs to the low gate leakage current of MOSFETs in a single deeply-scaled ultrahigh speed low-noise technology. Despite advances in the fabrication of MOS-HEMT devices and MMICs, the transistor microwave noise properties of GaInAs MOS-HEMT devices have not yet been reported. In the present study, the room temperature DC and wideband RF noise properties (8-50 GHz) of GaInAs channel MOS-HEMTs are characterized and contrasted to those of a 50 nm low-noise HEMT with the same channel composition/thickness and similar fT: at a given bias VDS = 0.5 V, the HEMT provides lower minimal noise figures (NFMIN) and higher associated gain. In contrast to HEMTs, the MOS-HEMTs particularly suffer from lower frequency noise contributions attributed to enhanced impact ionization. Remarkably, operation at VDS = 0.4 V to mitigate ionization enables MOS-HEMTs to match the HEMT wideband NFMIN performance despite a significantly poorer low-field channel mobility. The present MOS-HEMTs show the highest reported maximum oscillation frequency fMAX = 637 GHz for a measured gate length LG = 33 nm and a (2 × 15) μm width. Gate annealing is shown to be deleterious to the MOS-HEMT DC and noise properties.
  • Effects of Electrochemical Etching on InP HEMT Fabrication
    Item type: Conference Paper
    Saranovac, Tamara; Calvo Ruiz, Diego; Han, Daxin; et al. (2019)
    2019 International Conference on Compound Semiconductor MANufacturing TECHnology. Digest of Papers
  • High-Speed Steep-Slope GaInAs Impact Ionization MOSFETs (I-MOS) With SS = 1.25 mV/dec - Part I: Material and Device Characterization, DC Performance, and Simulation
    Item type: Journal Article
    Han, Daxin; Bonomo, Giorgio; Calvo Ruiz, Diego; et al. (2022)
    IEEE Transactions on Electron Devices
    Digital electronics power consumption evolved into a major concern: at the current pace, general-purpose computing energy consumption will exceed global energy production before 2045. The principal approach to curbing energy consumption in digital applications calls for ``steep-slope'' devices with an inverse subthreshold slope (SS) parameter well below the ``ln(10)·kT/q'' limit of conventional electronics (60 mV/dec at 300 K). Impact ionization MOSFETs (I-MOS) provide an avenue for steep-slope device realization. High-mobility narrow gap III-V semiconductor channel materials have not yet been investigated for I-MOS applications. We hereby report E-mode narrow bandgap GaInAs-based I-MOS devices with an SS of 1.25 mV/dec maintained over five orders of magnitude in drain current and Ion / Ioff ratios >10⁶ at 300 K (>10⁹ at 15 K) for a gate length of LG = 100 nm. Part I of this work focuses on the materials and device fabrication and analysis, device dc characterization, and modeling. The present GaInAs devices are the first I-MOS transistors to display a robust steep-slope effect at low voltages VDS < 1.9 V at 300 K and <1 V at 15 K. Part II describes the dynamic switching (including clarifications on the role of hysteresis) and RF characteristics of GaInAs I-MOS devices and benchmarks them with respect to other steep-slope technologies.
  • Impact of Reduced Gate‐to‐Source Spacing on InP HEMT Performance
    Item type: Journal Article
    Calvo Ruiz, Diego; Han, Daxin; Bonomo, Giorgio; et al. (2021)
    Physica Status Solidi A
    InP–based HEMTs with an offset gate enable higher maximum oscillation frequency (fMAX) values because of the resulting reduction in gate–to–source resistance. Following this approach, we show improved DC characteristics and cutoff frequencies (fT/fMAX > 410/710 GHz with LG = 50 nm) with respect to centered gate devices. However, HEMTs with an offset gate show degraded noise performances compared to centered gate devices because of a higher gate leakage current. Our results show that offsetting the gate closer to the source is not desirable for ultra–low noise performance.
Publications 1 - 8 of 8