Alessandro Novello

Last Name

Novello

First Name

Alessandro

ORCID

0000-0001-9072-865X

Organisational unit

09757 - Wang, Hua / Wang, Hua

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Publications 1 - 10 of 17

A 1.01 NEF Low-noise Amplifier Using Complementary Parametric Amplification
Atzeni, Gabriele; Guichemerre, Jérémy; Novello, Alessandro; et al. (2022)
IEEE Transactions on Circuits and Systems I: Regular Papers
This paper presents a discrete-time low-noise amplifier for miniaturized sensor nodes. Such amplifier achieves a noise efficiency factor of 1.01 and a power efficiency factor of 1.63, improving the noise efficiency of an analog front-end. The proposed preamplifier employs discrete-time parametric amplification by modulating the capacitance of a MOS varactor. The sampling noise is minimized by adopting a high oversampling ratio of the input voltage, leading to an input-referred noise of 520 nV rms in a 1 kHz bandwidth. Also, the power consumption is reduced by using a 34-phase stepwise charging technique. The multiphase soft-charging technique is implemented using multiple time-interleaved cells and allows to significantly reduce the current consumption without introducing any significant penalty in terms of additional noise or area occupation. A two-stage parametric amplifier is introduced to provide higher gain, and suppress the noise contribution of the following amplifier chain. The proposed two-stage complementary preamplifier is followed by a third continuous-time stage, that employs a current-reuse inverter-based architecture. The contribution to the total noise efficiency factor of such amplifier is attenuated by the gain of the previous two-stage parametric preamplifier. As a result, the third stage provides gain programmability, while degrading the NEF of the entire chain by less than 10%.
17.3 A 1.25GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators
Novello, Alessandro; Atzeni, Gabriele; Cristiano, Giorgio; et al. (2021)
Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2021 IEEE International Solid- State Circuits Conference (ISSCC)
Over the past years, the constant reduction in the size of consumer electronics has strengthened the demand for fully integrated power management circuits. Buck converters offer high efficiency, but they cannot satisfy the stringent size requirements because bulky off-chip inductors are required [1]. Switched-capacitor (SC) approaches provide fully integrated power management solutions; however, their power density is limited by the on-chip capacitance density [2]. Resonant switched capacitor (ReSC) converters need 3D die-stacked inductors or PCB-integrated inductors to achieve appropriate power density values, posing challenges for monolithic integration [3]. A fully integrated ReSC has been presented [4], which implements an on-chip resonator, avoiding any external or 3D stacked passive components. However, the switching losses associated with the four transistors driving the resonator limit the switching frequency to 10s of MHz, bounding the power density scaling to 0.097W/mm 2.© 2021 IEEE.
A 2.3GHz Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators achieving 78.1% Efficiency in 22nm FDSOI CMOS
Novello, Alessandro; Atzeni, Gabriele; Cristiano, Giorgio; et al. (2021)
IEEE Solid-State Circuits Letters
This letter introduces a fully integrated DC-DC converter based on electromagnetically coupled class-D LC oscillators featuring on-chip stacked 8-shaped transformers in a 22nm FDSOI CMOS process. The GHz-range resonant frequency of the proposed converter enables high integration of the passive components, achieving up to 3.2W/mm2 power density. The on-chip 8-shaped stacked transformers reach 16.9 quality factor and 0.91 coupling coefficient, demonstrating 78.1% converter efficiency. Furthermore, the twisted nature of the 8-shaped transformers introduces a magnetic field cancellation mechanism that minimizes the parasitic coupling between the transformers, saving 25% area in one single converter unit and 47% in the converter array, with respect a spiral transformer implementation. In addition, the field intensity is reduced by 27dB outside of the transformer borders compared with a spiral implementation, which helps to mitigate issues such as parasitic magnetic coupling with neighbouring circuits and EMI.
A 1.25-GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators
Novello, Alessandro; Atzeni, Gabriele; Künzli, Jonas; et al. (2021)
IEEE Journal of Solid-State Circuits
Fully integrated power management circuits are promising candidates to provide small form factors and meet high power density demand of modern computing platforms. This article presents a new fully integrated dc-dc converter topology based on electromagnetically coupled class-D LC oscillators that enables up to 2.5 GHz switching frequency, allowing aggressive scaling of the on-chip passives. On-chip transformers and flying capacitors are designed to electromagnetically couple the two oscillators, and gigahertz-range switching frequency is achieved by the quasi-adiabatic switching of the parasitic capacitors. The proposed converter is implemented in a 0.18-μm CMOS process occupying 1.61 mm² for 7.8 nH inductance (high efficiency version) and 0.37 mm² for 3.1 nH (high power density version), achieving 1 W/mm² peak power density. This work also proposes a duty-cycling scheme that improves the efficiency under light loads, which stays close to the peak from 4 μW up to 0.5 W, and in continuous operation mode the output voltage ripple is 12 mV without attaching any output capacitor thanks to the four-phase electromagnetic power delivery scheme.
Design Challenges of Fully Integrated DC-DC Converters for Modern Power Delivery Architectures
Song, Suyang; Novello, Alessandro; Jang, Taekwang (2024)
IEEE Solid-State Circuits Letters
This letter presents recent design challenges of modern power delivery architectures and circuit techniques for them. Recent computational loads impose significant power output demands on DC-DC converters while ever-shrinking Internet of Things (IoT) systems demand DC-DC converters with small footprints. Consequently, fully integrated DC-DC converters are highly desirable in contemporary power delivery architectures thanks to their compact footprint, high power density, and fast output regulation. However, numerous challenges exist in fully integrating DC-DC converters, necessitating the investigation of various circuit topologies and complex regulation schemes to ensure proper operation and versatility.
An Impedance-boosted Switched-capacitor Low-noise Amplifier Achieving 0.4 NEF
Atzeni, Gabriele; Incandela, Rosario; Ji, Youngwoo; et al. (2022)
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
This paper presents an impedance-boosted analog front-end (AFE) for mm-scale ultra-low power sensor nodes. The proposed AFE employs a discrete-time low noise amplifier (LNA) based on noise-efficient switched-capacitor stages. The input impedance, ZIN, is boosted through a 27-step multiphase soft-charging technique of the bottom-plate capaci-tance, achieving ZIN > 10 MΩ at 4.5 MHz sampling frequency. The LNA achieves 0.4 NEF and 0.15 PEF, the smallest values reported to date, while consuming 0.28 μW.
A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving 7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature Range
Ji, Youngwoo; Liao, Jiawei; Arjmandpour, Sina; et al. (2022)
Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2022 IEEE International Solid- State Circuits Conference (ISSCC)
With the development of various miniaturized IoT applications, the need for on-chip time management has been growing rapidly. An on-chip RC oscillator is one of the promising candidates since it can be fully integrated with standard CMOS technology. Typically, an RC oscillator is implemented with a comparator that periodically resets a capacitor voltage at an interval defined by a fraction of the RC time constant to generate a stable output frequency. Therefore, the RC time constant needs to be invariant to the supply voltage and temperature changes. Also, the comparator must be high power, so that its temperature-dependent delay becomes negligible compared to the RC time constant.
An Energy-Efficient Low-Noise Complementary Parametric Amplifier Achieving 0.89 NEF
Atzeni, Gabriele; Guichemerre, Jérémy; Novello, Alessandro; et al. (2020)
2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)
This paper presents an energy-efficient low-noise amplifier, achieving 0.89 noise efficiency factor (NEF) using discrete-time parametric amplification. A complementary parametric input stage is proposed to eliminate any DC shift between the input and output voltage levels. The power consumption is reduced by adopting a 34-phase stepwise charging technique and the sampling-induced input-referred noise is minimized by oversampling the input signal. Time- interleaving multiple parallel stages allows implementing the multiphase soft-charging scheme without causing any significant penalty in terms of area. A second current-reuse inverter-based amplification stage is designed to provide high gain, while its contribution to the total input-referred noise is attenuated by the preamplifier gain. The overall NEF is 1.76 and the total power consumption is 1.73 µW. © 2020 IEEE.
A 1.5GHz Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators and Resonant LC Flying Impedance achieving 4.1W/mm2 Peak Power Density and 77% Peak Efficiency
Novello, Alessandro; Atzeni, Gabriele; Keller, Tim; et al. (2024)
IEEE Solid-State Circuits Letters
This letter introduces a fully integrated DC-DC converter based on electromagnetically coupled class-D LC oscillators (EMLC) manufactured in a 22nm FDSOI CMOS process. The proposed converter implements a resonant LC flying impedance that improves the EMLC output resistance by accomplishing a resonant charge transfer between the flying capacitor CFLY and the load capacitor CO. This design achieves 77% peak efficiency and 4.1W/mm2 peak power density in a total area of 0.33mm2. The output voltage is regulated with a duty cycling scheme from 0.003W/mm2 up to 2.1W/mm2 with <2% efficiency loss.
A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM-Controlled Frequency-Locked Loops
Cristiano, Giorgio; Liao, Jiawei; Novello, Alessandro; et al. (2020)
2020 IEEE Symposium on VLSI Circuits
This paper presents an on-chip timer composed of two DSM-controlled RC oscillators, locked through a non-linearity aware digital dual phase-locked loop. The proposed design achieves an accurate temperature coefficient below 8.7ppm/degrees C from 10 samples from two different wafer lots with only one-point calibration and an Allan deviation floor of 4ppm. The power consumption is 694nW at 116kHz.

Publications 1 - 10 of 17

Alessandro Novello

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