Gabriele Atzeni

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Atzeni

First Name

Gabriele

ORCID

0000-0003-0346-4356

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Publications 1 - 10 of 23

A 1.01 NEF Low-noise Amplifier Using Complementary Parametric Amplification
Atzeni, Gabriele; Guichemerre, Jérémy; Novello, Alessandro; et al. (2022)
IEEE Transactions on Circuits and Systems I: Regular Papers
This paper presents a discrete-time low-noise amplifier for miniaturized sensor nodes. Such amplifier achieves a noise efficiency factor of 1.01 and a power efficiency factor of 1.63, improving the noise efficiency of an analog front-end. The proposed preamplifier employs discrete-time parametric amplification by modulating the capacitance of a MOS varactor. The sampling noise is minimized by adopting a high oversampling ratio of the input voltage, leading to an input-referred noise of 520 nV rms in a 1 kHz bandwidth. Also, the power consumption is reduced by using a 34-phase stepwise charging technique. The multiphase soft-charging technique is implemented using multiple time-interleaved cells and allows to significantly reduce the current consumption without introducing any significant penalty in terms of additional noise or area occupation. A two-stage parametric amplifier is introduced to provide higher gain, and suppress the noise contribution of the following amplifier chain. The proposed two-stage complementary preamplifier is followed by a third continuous-time stage, that employs a current-reuse inverter-based architecture. The contribution to the total noise efficiency factor of such amplifier is attenuated by the gain of the previous two-stage parametric preamplifier. As a result, the third stage provides gain programmability, while degrading the NEF of the entire chain by less than 10%.
Noise-Efficient Circuits and Systems for Biomedical and Environmental Sensing Applications
Atzeni, Gabriele (2024)
17.3 A 1.25GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators
Novello, Alessandro; Atzeni, Gabriele; Cristiano, Giorgio; et al. (2021)
Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2021 IEEE International Solid- State Circuits Conference (ISSCC)
Over the past years, the constant reduction in the size of consumer electronics has strengthened the demand for fully integrated power management circuits. Buck converters offer high efficiency, but they cannot satisfy the stringent size requirements because bulky off-chip inductors are required [1]. Switched-capacitor (SC) approaches provide fully integrated power management solutions; however, their power density is limited by the on-chip capacitance density [2]. Resonant switched capacitor (ReSC) converters need 3D die-stacked inductors or PCB-integrated inductors to achieve appropriate power density values, posing challenges for monolithic integration [3]. A fully integrated ReSC has been presented [4], which implements an on-chip resonator, avoiding any external or 3D stacked passive components. However, the switching losses associated with the four transistors driving the resonator limit the switching frequency to 10s of MHz, bounding the power density scaling to 0.097W/mm 2.© 2021 IEEE.
A 2.3GHz Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators achieving 78.1% Efficiency in 22nm FDSOI CMOS
Novello, Alessandro; Atzeni, Gabriele; Cristiano, Giorgio; et al. (2021)
IEEE Solid-State Circuits Letters
This letter introduces a fully integrated DC-DC converter based on electromagnetically coupled class-D LC oscillators featuring on-chip stacked 8-shaped transformers in a 22nm FDSOI CMOS process. The GHz-range resonant frequency of the proposed converter enables high integration of the passive components, achieving up to 3.2W/mm2 power density. The on-chip 8-shaped stacked transformers reach 16.9 quality factor and 0.91 coupling coefficient, demonstrating 78.1% converter efficiency. Furthermore, the twisted nature of the 8-shaped transformers introduces a magnetic field cancellation mechanism that minimizes the parasitic coupling between the transformers, saving 25% area in one single converter unit and 47% in the converter array, with respect a spiral transformer implementation. In addition, the field intensity is reduced by 27dB outside of the transformer borders compared with a spiral implementation, which helps to mitigate issues such as parasitic magnetic coupling with neighbouring circuits and EMI.
An Energy-Efficient Impedance-Boosted Discrete-Time Amplifier Achieving 0.34 Noise Efficiency Factor and 389 MΩ Input Impedance
Atzeni, Gabriele; Livanelioglu, Can; Recchioni, Lavinia; et al. (2023)
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
This paper presents a noise-efficient analog front end (AFE) for low-power sensor systems. The proposed AFE employs a low-noise amplifier based on series-parallel converters whose input impedance is boosted to 389 MΩ (39× improvement compared to prior work) using an input-resistance boosting loop and a capacitive positive feedback loop. The AFE achieves the lowest reported noise efficiency factor (NEF) and power efficiency factor (PEF) of 0.34 and 0.1, respectively, while consuming 370 nW.
A 1.25-GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators
Novello, Alessandro; Atzeni, Gabriele; Künzli, Jonas; et al. (2021)
IEEE Journal of Solid-State Circuits
Fully integrated power management circuits are promising candidates to provide small form factors and meet high power density demand of modern computing platforms. This article presents a new fully integrated dc-dc converter topology based on electromagnetically coupled class-D LC oscillators that enables up to 2.5 GHz switching frequency, allowing aggressive scaling of the on-chip passives. On-chip transformers and flying capacitors are designed to electromagnetically couple the two oscillators, and gigahertz-range switching frequency is achieved by the quasi-adiabatic switching of the parasitic capacitors. The proposed converter is implemented in a 0.18-μm CMOS process occupying 1.61 mm² for 7.8 nH inductance (high efficiency version) and 0.37 mm² for 3.1 nH (high power density version), achieving 1 W/mm² peak power density. This work also proposes a duty-cycling scheme that improves the efficiency under light loads, which stays close to the peak from 4 μW up to 0.5 W, and in continuous operation mode the output voltage ripple is 12 mV without attaching any output capacitor thanks to the four-phase electromagnetic power delivery scheme.
A Light Tolerant Neural Recording IC for Near-Infrared-Powered Free Floating Motes
Lim, Jongyup; Lee, Jungho; Moon, Eunseong; et al. (2021)
2021 Symposium on VLSI Circuits
A key challenge for near-infrared (NIR) powered neural recording ICs is to maintain robust operation in the presence of parasitic short circuit current from junction diodes when exposed to light. This is especially so when intentional currents are kept small to reduce power consumption. We present a neural recording IC that is tolerant up to 300 µW/mm 2 light exposure (above tissue limit) and consumes 0.57 µW at 38°C, making it lowest power among standalone motes while incorporating on-chip feature extraction and individual gain control.
19.10 A 4.6GHz 63.3fsrms PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving −255.2dB FoMJ Including the XO Power and Noise
Livanelioglu, Can; He, Long; Gong, Jiang; et al. (2025)
2025 IEEE International Solid-State Circuits Conference (ISSCC)
With the advancements in low-noise-circuit techniques, phase-locked loops (PLLs) have been pushing their jitter figure of merits (FoMJ) to −260 and −255dB for integer- and fractional-N modes, respectively. The in-band noise and power are improved with sub-sampling, over-sampling, and digital techniques [1]–[6], while advanced LC-oscillator methods [7]–[9] reduce their power and out-of-band noise, achieving under 50fsrms integrated jitter with a few mW of power consumption. However, the power and noise optimizations historically overlook the full frequency-generation-and-synthesis chain, including the crystaloscillator (XO) driver, reference buffer, and the PLL.
An Impedance-boosted Switched-capacitor Low-noise Amplifier Achieving 0.4 NEF
Atzeni, Gabriele; Incandela, Rosario; Ji, Youngwoo; et al. (2022)
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
This paper presents an impedance-boosted analog front-end (AFE) for mm-scale ultra-low power sensor nodes. The proposed AFE employs a discrete-time low noise amplifier (LNA) based on noise-efficient switched-capacitor stages. The input impedance, ZIN, is boosted through a 27-step multiphase soft-charging technique of the bottom-plate capaci-tance, achieving ZIN > 10 MΩ at 4.5 MHz sampling frequency. The LNA achieves 0.4 NEF and 0.15 PEF, the smallest values reported to date, while consuming 0.28 μW.
A Wireless Neural Stimulator IC for Cortical Visual Prosthesis
Lee, Jungho; Letner, Joseph; Lim, Jongyup; et al. (2023)
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
We propose a 0.25 x 0.25 x 0.3 mm (∼0.02 mm 3 ) optically powered mote for visual cortex stimulation to restore vision. Up to 1024 implanted motes can be individually addressed. The complete StiMote system was confirmed fully functional when optically powered and cortex stimulation was confirmed in-vivo with a live rat brain.

Publications 1 - 10 of 23

Gabriele Atzeni

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