Davide Cittanti


Last Name

Cittanti

First Name

Davide

ORCID

0000-0002-5816-1320

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2022 - 20232
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Publications1 - 2 of 2
  • A Simplified Hard-Switching Loss Model for Fast-Switching Three-Level T-Type SiC Bridge-Legs
    Item type: Journal Article
    Cittanti, Davide; Gammeter, Cristoph; Huber, Jonas; et al. (2022)
    Electronics
    Hard-switching losses in three-level T-type (3LTT) bridge-legs cannot be directly estimated from datasheet energy loss curves, which are given for symmetric two-level half-bridge configurations only. The commutations in a 3LTT bridge-leg occur between semiconductors with different blocking voltages and/or current ratings, and involve a third semiconductor device in the switching transition, which contributes additional capacitive losses. This paper, therefore, describes a simplifed approach to estimate a lower bound for the hard-switching losses of 3LTT bridge-legs (note that the approach is applicable to other three-level topolgies as well). In view of the very fast switching speeds of wide-bandgap semiconductors, the model neglects voltage/current overlap losses and considers only the dominating charge-related loss contributions (semiconductor output capacitances, body diode reverse-recovery charge), thus requiring minimal information from datasheets. A direct experimental verification with an 800 V DC-link 3LTT bridge-leg (1200 V and 650 V SiC MOSFETs) operating with output currents up to 25 A confirms the good accuracy of the simplified switching-loss model.
  • Detailed Modeling and In-Situ Calorimetric Verification of Three-Phase Sparse NPC Converter Power Semiconductor Losses
    Item type: Journal Article
    Zhang, Daifei; Cittanti, Davide; Sun, Pengpeng; et al. (2023)
    IEEE Journal of Emerging and Selected Topics in Power Electronics
    The three-phase (3- Φ) three-level (3-L) sparse neutral point clamped converter (SNPCC) combines a 3-L matrix stage and a 3- Φtwo-level (2-L) inverter stage to generate 3-L switched output voltages with a reduced transistor count (10 instead of 12 or 18) compared with the classical 3-L NPCC or 3-L active NPCC structure, targeting variable-speed drive (VSD) systems with low ripple of the motor phase currents or bidirectional 3- Φ power factor correcting (PFC) rectifier systems with reduced boost inductor volume. This article analyzes and experimentally characterizes the performance of an IGBT-based 3- Φ 3-L SNPCC and describes, for the first time, a hybrid current commutation effect between inverter-stage diodes and matrix-stage IGBTs that occurs when operating with lower modulation indices and leads to increased switching losses (up to 20% ). The proposed new semiconductor loss modeling approach accounts for this effect successfully, which is verified ( < 10% error) on an 800- Vdc, 7.5-kW SNPCC hardware demonstrator using a new in-situ calorimetric method that facilitates accurate stage-level semiconductor loss measurements. Heat spreading effects caused by the asymmetrical losses injection and thermal decoupling between two in-situ loss measurement blocks are carefully checked with finite-element method (FEM) simulations. Furthermore, an experimental evaluation of common-mode (CM) and differential-mode (DM) high-frequency (HF) voltage-time area ripples (as a generic measure for the required filtering effort) for three typical symmetrical and asymmetrical modulation switching state sequences is provided together with the semiconductor loss characterization. Utilizing a low-switching-loss asymmetric modulation scheme that operates the 3-L matrix stage and the 2-L inverter stage with the effective switching frequencies of 16 kHz and 5.3 kHz, respectively, the 3-L SNPCC demonstrator finally achieves a high rated power (7.5 kW, load current phase shift φ = 0 ) semiconductor efficiency of 98.8%.
Publications1 - 2 of 2