Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC
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Date
2025-02
Publication Type
Journal Article
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Abstract
The ongoing integration of advanced functionalities in contemporary system-on-chips (SoCs) poses significant challenges related to memory bandwidth, capacity, and thermal stability. These challenges are further amplified with the advancement of artificial intelligence (AI), necessitating enhanced memory and interconnect bandwidth and latency. This article presents a comprehensive study encompassing architectural modifications of an interconnect-dominated many-core SoC targeting the significant increase of intermediate, on-chip cache memory bandwidth and access latency tuning. The proposed SoC has been implemented in 3-D using A10 nanosheet technology and early thermal analysis has been performed. Our workload simulations reveal, respectively, up to 12-and 2.5-fold acceleration in the 64-core and 16-core versions of the SoC. Such speed-up comes at 40% increase in die-area and a 60% rise in power dissipation when implemented in 2-D. In contrast, the 3-D counterpart not only minimizes the footprint but also yields 20% power savings, attributable to a 40% reduction in wirelength. The article further highlights the importance of pipeline restructuring to leverage the potential of 3-D technology for achieving lower latency and more efficient memory access. Finally, we discuss the thermal implications of various 3-D partitioning schemes in High Performance Computing (HPC) and mobile applications. Our analysis reveals that, unlike high-power density HPC cases, 3-D mobile case increases T-max only by 2 degree celsius -3degree celsius compared to 2-D, while the HPC scenario analysis requires multiconstrained efficient partitioning for 3-D implementations.
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published
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Volume
33 (2)
Pages / Article No.
346 - 357
Publisher
IEEE
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Subject
Bandwidth; Memory management; Integrated circuit interconnections; Thermal analysis; Stacking; System performance; Pipelines; Very large scale integration; Tuning; Thermal stability; 3-D integration; interconnect; latency; logic-on-logic (LoL); many-core; power; performance and area (PPA); system analysis; system and technology co-optimization (STCO); thermal
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03996 - Benini, Luca / Benini, Luca