Skip It: Take Control of Your Cache!
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Author / Producer
Date
2024-04
Publication Type
Conference Paper
ETH Bibliography
yes
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Abstract
Mechanisms to explicitly manage the presence of data in caches are fundamental for the correctness and performance of modern systems. These operations, while critical, often incur significant performance penalties even when carefully used. Moreover, these mechanisms are implemented in proprietary and often undocumented hardware, so research into optimizations and novel designs is mostly limited to slow, simplified software simulations. In this paper, we design microarchitectural extensions to support two types of user-controlled cache writebacks to main memory. Furthermore, we propose Skip It, a mechanism built on top of our extensions that substantially reduces redundant writebacks. We implemented these designs on the open-source BOOM out-of-order RISC-V CPU. The performance in hardware is ≈ 100 cycles which favorably compares to similar operations in commercially available server-class platforms. In addition, Skip It performs as well as or better than state-of-the-art software techniques for avoiding unnecessary writebacks.
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Publication status
published
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Editor
Book title
Volume
2
Pages / Article No.
1077 - 1094
Publisher
Association for Computing Machinery
Event
29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2024)
Edition / version
Methods
Software
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Date collected
Date created
Subject
microarchitecture; cache coherence; out-of-order multicore; cacheline flush; fence; non-volatile memory; FPGA simulation; RISC-V
Organisational unit
03506 - Alonso, Gustavo / Alonso, Gustavo