Utopia: Efficient Address Translation using Hybrid Virtual-to-Physical Address Mapping


Loading...

Date

2022-12-06

Publication Type

Working Paper

ETH Bibliography

yes

Citations

Altmetric

Data

Abstract

The conventional virtual-to-physical address mapping scheme enables a virtual address to flexibly map to any physical address. This flexibility necessitates large data structures to store virtual-to-physical mappings, which incurs significantly high address translation latency and translation-induced interference in the memory hierarchy, especially in data-intensive workloads. Restricting the address mapping so that a virtual address can map to only a specific set of physical addresses can significantly reduce the overheads associated with the conventional address translation by making use of compact and more efficient translation structures. However, restricting the address mapping flexibility across the entire main memory severely limits data sharing across different processes and increases memory under-utilization. In this work, we propose Utopia, a new hybrid virtual-to-physical address mapping scheme that allows both flexible and restrictive hash-based address mapping schemes to co-exist in a system. The key idea of Utopia is to manage the physical memory using two types of physical memory segments: restrictive segments and flexible segments. A restrictive segment uses a restrictive, hash-based address mapping scheme to map the virtual addresses to only a specific set of physical addresses and enable faster address translation using compact and efficient translation structures. A flexible segment is similar to the conventional address mapping scheme and provides full virtual-to-physical address mapping flexibility. By mapping data to a restrictive segment, Utopia enables faster address translation with lower translation-induced interference whenever a flexible address mapping is not necessary. Our evaluation using 11 data-intensive workloads shows that Utopia improves performance by 32% on average in single-core workloads over the baseline four-level radix-tree page table design.

Publication status

published

Editor

Book title

Journal / series

Volume

Pages / Article No.

Publisher

Cornell University

Event

Edition / version

v.2

Methods

Software

Geographic location

Date collected

Date created

Subject

Hardware Architecture (cs.AR); FOS: Computer and information sciences

Organisational unit

09483 - Mutlu, Onur / Mutlu, Onur check_circle

Notes

Funding

Related publications and datasets