Analysis and Comparative Evaluation of Stacked-Transistor Half-Bridge Topologies Implemented with 14 nm Bulk CMOS Technology
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Author / Producer
Date
2017
Publication Type
Conference Paper
ETH Bibliography
yes
Citations
Altmetric
OPEN ACCESS
Data
Rights / License
Permanent link
Publication status
published
External links
Editor
Book title
2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL)
Journal / series
Volume
Pages / Article No.
8013307
Publisher
IEEE
Event
2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL)
Edition / version
Methods
Software
Geographic location
Date collected
Date created
Subject
IVR; CMOS; Stacked transistors; Half-bridge; Multiphase; 14 nm technology
Organisational unit
03573 - Kolar, Johann W. (emeritus) / Kolar, Johann W. (emeritus)
Notes
Funding
619488 - Manufacturing of Modular Interposer providing scalable Heat Removal, Power Delivery and Optical Signaling (EC)