Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications
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Author / Producer
Date
2017
Publication Type
Conference Paper
ETH Bibliography
yes
Citations
Altmetric
METADATA ONLY
Data
Rights / License
Permanent link
Publication status
published
External links
Editor
Book title
2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Journal / series
Volume
Pages / Article No.
8106976
Publisher
IEEE
Event
27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017)
Edition / version
Methods
Software
Geographic location
Date collected
Date created
Subject
RISC-V; energy efficiency; area optimized; ultra-low-power; open-source; core; microprocessor; internet-of-things
Organisational unit
03996 - Benini, Luca / Benini, Luca
02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.
02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory
Notes
Funding
162524 - MicroLearn: Micropower Deep Learning (SNF)