Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
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Date
2025
Publication Type
Other Conference Item
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yes
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Abstract
The rapid growth of AI-based Internet-of-Things applications in creased the demand for high-performance edge processing engines on a low-power budget and tight area constraints. As a conse quence, vector processor architectures, traditionally designed for high-performance computing (HPC), made their way into edge devices, promising high utilization of floating-point units (FPUs) and low power consumption. However, vector processors can only exploit a single dimension of parallelism, leading to expensive ac cesses to the vector register file (VRF) when performing matrix computations, which are pervasive in AI workloads. To overcome these limitations while guaranteeing programmability, many re searchers and companies are developing dedicated instructions for a more efficient matrix multiplication (MatMul) execution. In this context, we propose Quadrilatero, an open-source RISC-V pro grammable systolic array coprocessor for low-power edge appli cations that implements a streamlined matrix ISA extension. We evaluate the post-synthesis power, performance, and area (PPA) metrics of Quadrilatero in a mature 65-nm technology node, show ing that it requires only 0.65 𝑚𝑚2 and that it can reach up to 99.4% of FPU utilization. Compared to a state-of-the-art open-source RISC V vector processor and a hybrid vector-matrix processor optimized for embedded applications, Quadrilatero improves area efficiency and energy efficiency by up to 77% and 15%, respectively.
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published
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Book title
CF '25 Companion: Proceedings of the 22nd ACM International Conference on Computing Frontiers: Workshops and Special Sessions
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Volume
Pages / Article No.
66 - 69
Publisher
Association for Computing Machinery
Event
22nd ACM International Conference on Computing Frontiers: Workshops and Special Sessions
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Methods
Software
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Date created
Subject
Systolic arrays; RISC-V; Matrix ISA; Matrix multiplication
Organisational unit
03996 - Benini, Luca / Benini, Luca
Notes
Extended Abstract.
Funding
101120726 - A network of excellence for distributed, trustworthy, efficient and scalable AI at the Edge (SBFI)