Trap-aware compact modeling and power-performance assessment of III-V tunnel FET
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Author / Producer
Date
2019-02-11
Publication Type
Conference Paper
ETH Bibliography
yes
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Publication status
published
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Book title
Proceedings of the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2018)
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Pages / Article No.
8640183
Publisher
IEEE
Event
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2018)
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Date collected
Date created
Subject
III-V tunnel FET; compact modeling; SPICE simulation; device traps; logic circuits; power-performance metrics
Organisational unit
Notes
Funding
619509 - Energy Efficient Tunnel FET Switches and Circuits (EC)