fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning
EMBARGOED UNTIL 2025-12-31
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Author / Producer
Date
2025
Publication Type
Conference Paper
ETH Bibliography
yes
Citations
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EMBARGOED UNTIL 2025-12-31
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Abstract
Microarchitectural timing channels exploit information leak age between security domains that should be isolated, bypassing the operating system’s security boundaries. These channels result from contention for shared microarchitectural state. In the RISC-V instruction set, the temporal fence instruction (fence.t) was proposed to close timing channels by providing an operating system with the means to temporally partition microarchitectural state inexpensively in simple in-order cores. This work explores challenges with fence.t in superscalar out-of-order cores featuring large and pervasive microarchitectural state. To overcome these challenges, we propose a novel SW-supported temporal fence (fence.t.s), which reuses existing mechanisms and supports advanced microarchitectural features, enabling full timing channel protection of an exemplary out-of-order core (OpenC910) at negligible hardware costs and a minimal performance impact of 1.0 %.
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Publication status
published
External links
Book title
Applications in Electronics Pervading Industry, Environment and Society
Journal / series
Volume
1369
Pages / Article No.
269 - 276
Publisher
Springer
Event
12th International Conference on Applications in Electronics Pervading Industry, Environment and Society (ApplePies 2024)
Edition / version
Methods
Software
Geographic location
Date collected
Date created
Subject
Organisational unit
03996 - Benini, Luca / Benini, Luca
Notes
Conference lecture held on September 20, 2024.
Funding
101095947 - Together for RISc-V Technology and ApplicatioNs (SBFI)