Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
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Author / Producer
Date
2024
Publication Type
Conference Paper
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yes
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Abstract
Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction (LVP) and Memory Renaming (MRN) mitigate load data dependence by predicting the data value of a load instruction. However, they fail to mitigate load resource dependence as the predicted load instruction gets executed nonetheless (even on a correct prediction), which consumes hard-to-scale pipeline resources that otherwise could have been used to execute other load instructions.
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published
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Book title
2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)
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Pages / Article No.
88 - 102
Publisher
IEEE
Event
51st ACM/IEEE Annual International Symposium on Computer Architecture (ISCA 2024)
Edition / version
Methods
Software
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Organisational unit
09483 - Mutlu, Onur / Mutlu, Onur
Notes
Conference Presentation held on July 1, 2024.