Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms
dc.contributor.author
Paolucci, Pier S.
dc.contributor.author
Biagioni, Andrea
dc.contributor.author
Murillo, Luis G.
dc.contributor.author
Rousseau, Frederic
dc.contributor.author
Schor, Lars
dc.contributor.author
Tosoratto, Laura
dc.contributor.author
Bacivarov, Iuliana
dc.contributor.author
Buecs, Robert L.
dc.contributor.author
Deschamps, Clément
dc.contributor.author
El Antably, Ashraf
dc.contributor.author
Ammendola, Roberto
dc.contributor.author
Fournel, Nicolas
dc.contributor.author
Frezza, Ottorino
dc.contributor.author
Leupers, Rainer
dc.contributor.author
Lo Cicero, Francesca
dc.contributor.author
Lonardo, Alessandro
dc.contributor.author
Martinelli, Michele
dc.contributor.author
Pastorelli, Elena
dc.contributor.author
Rai, Devendra
dc.contributor.author
Rossetti, Davide
dc.contributor.author
Simula, Francesco
dc.contributor.author
Thiele, Lothar
dc.contributor.author
Vicini, Piero
dc.contributor.author
Weinstock, Jan H.
dc.date.accessioned
2017-06-11T22:57:25Z
dc.date.available
2017-06-11T22:57:25Z
dc.date.issued
2016-09
dc.identifier.issn
1383-7621
dc.identifier.other
10.1016/j.sysarc.2015.11.008
dc.identifier.uri
http://hdl.handle.net/20.500.11850/110035
dc.language.iso
en
dc.publisher
Elsevier
dc.subject
Many-tile hardware architectures
dc.subject
Many-tile simulation
dc.subject
Many-process applications
dc.subject
Embedded systems
dc.subject
High performance computing
dc.subject
Dynamic multimedia application
dc.subject
Spiking neural network
dc.subject
Synaptic plasticity
dc.subject
Fault tolerance
dc.subject
Task migration
dc.subject
Application mapping
dc.subject
Hardware dependent Software
dc.subject
Distributed network processor
dc.subject
3D toroidal interconnect
dc.title
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms
dc.type
Journal Article
ethz.journal.title
Journal of systems architecture
ethz.journal.volume
69
ethz.journal.abbreviated
J. systems archit.
ethz.pages.start
29
ethz.pages.end
53
ethz.notes
Published online 24 November 2015.
ethz.identifier.wos
ethz.identifier.nebis
001650404
ethz.publication.status
published
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02640 - Inst. f. Technische Informatik und Komm. / Computer Eng. and Networks Lab.::03429 - Thiele, Lothar (emeritus) / Thiele, Lothar (emeritus)
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02640 - Inst. f. Technische Informatik und Komm. / Computer Eng. and Networks Lab.::03429 - Thiele, Lothar (emeritus) / Thiele, Lothar (emeritus)
ethz.date.deposited
2017-06-11T22:57:53Z
ethz.source
ECIT
ethz.identifier.importid
imp593653ecc75dd35477
ethz.ecitpid
pub:171184
ethz.eth
yes
ethz.availability
Metadata only
ethz.rosetta.installDate
2017-07-14T17:13:31Z
ethz.rosetta.lastUpdated
2023-02-06T13:11:43Z
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true
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true
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