A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
Publication status
publishedExternal links
Book title
Proceedings of the 41st European Solid-State Circuits Conference (ESSCIRC 2015)Pages / Article No.
Publisher
IEEEEvent
More
Show all metadata