An output-capacitor-free adaptively biased LDO regulator with robust frequency compensation in 0.13μm CMOS for SoC application

Abstract

This paper presents a fast-response low-dropout (LDO) regulator using a current feedback loop to realize an adaptive biasing error amplifier. With the proposed current feedback loop, the LDO regulator achieves 34dB higher loop gain, 46% faster transient response, and about 12dB higher power supply rejection above 1MHz than the one with fixed biasing. The adaptively-biased LDO regulator is compensated by a simple Miller compensation using adaptive nulling resistor (SMCANR). The proposed compensation network can realize robust frequency compensation and reduce voltage spikes during load transients. An expanded stability analysis using the Routh-Hurwitz criterion gives designers additional freedom for a stable design. Designed in a 0.13μm CMOS technology for a minimum dropout voltage of 200mV, the LDO regulator supplies 1.2V at 98.2% current efficiency and 10mA load current.