Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor

Mutlu, Onur; Belgard, Rich; Gross, Thomas; Jouppi, Norman R.; Hennessy, John L.; Przybylski, Steven; Rowen, Chris; Patt, Yale N.; Hwu, Wen-mei W.; Melvin, Stephen W.; Shebanow, Michael C.; Yeh, Tse-Yu; Wolfe, Andy

doi:10.1109/MM.2016.66

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Author

Date

2016

Type

Journal Article

Citations

Cited 2 times in Web of Science

Cited 2 times in Scopus

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yes

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Publication status

published

External links

https://doi.org/10.1109/MM.2016.66

Journal / series

IEEE Micro

Volume

36(4)

Pages / Article No.

70 - 85

Publisher

IEEE

Subject

CISC; Test of time; TOT; Award; Microarchitecture; HPS; High performance substrate; Two-level branch predictor; Compressed Code RISC Processor; RISC

Organisational unit

09483 - Mutlu, Onur / Mutlu, Onur

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Citations

Cited 2 times in Web of Science

Cited 2 times in Scopus

ETH Bibliography

yes

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