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dc.contributor.author
Carrillo-Nuñez, Hamilton
dc.contributor.author
Stieger, Christian
dc.contributor.author
Luisier, Mathieu
dc.contributor.author
Schenk, Andreas
dc.date.accessioned
2017-06-12T18:06:43Z
dc.date.available
2017-06-12T18:06:43Z
dc.date.issued
2016
dc.identifier.isbn
978-1-5090-3902-9
dc.identifier.isbn
978-1-5090-3901-2
dc.identifier.isbn
978-1-5090-3903-6
dc.identifier.other
10.1109/IEDM.2016.7838417
dc.identifier.uri
http://hdl.handle.net/20.500.11850/125430
dc.language.iso
en
dc.publisher
IEEE
dc.title
Performance predictions of single-layer InV double-gate n- and p-type field-effect transistors
dc.type
Conference Paper
ethz.book.title
2016 IEEE International Electron Devices Meeting (IEDM)
ethz.pages.start
14.5.1
ethz.pages.end
14.5.4
ethz.event
IEEE International Electron Devices Meeting (IEDM)
ethz.event.location
San Francisco, CA, USA
ethz.event.date
December 3-7, 2016
ethz.notes
Also published by: http://dx.doi.org/10.3929/ethz-a-010810577.
ethz.identifier.scopus
ethz.publication.place
Piscataway, NJ
ethz.publication.status
published
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::03925 - Luisier, Mathieu / Luisier, Mathieu
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::03925 - Luisier, Mathieu / Luisier, Mathieu
ethz.date.deposited
2017-06-12T18:07:23Z
ethz.source
ECIT
ethz.identifier.importid
imp5936550ff1dbd93442
ethz.ecitpid
pub:188034
ethz.eth
yes
ethz.availability
Metadata only
ethz.rosetta.installDate
2017-07-12T18:46:15Z
ethz.rosetta.lastUpdated
2018-11-03T01:19:31Z
ethz.rosetta.versionExported
true
ethz.COinS
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