Module generation in VLSI design
a graph theoretical approach
dc.contributor.author
Heeb, Hans-Rudolf
dc.contributor.supervisor
Declercq, Michel
dc.contributor.supervisor
Fichtner, Wolfgang
dc.date.accessioned
2017-06-13T00:52:41Z
dc.date.available
2017-06-13T00:52:41Z
dc.date.issued
1989
dc.identifier.uri
http://hdl.handle.net/20.500.11850/140380
dc.identifier.doi
10.3929/ethz-a-000599219
dc.format
application/pdf
dc.language.iso
en
dc.publisher
ETH Zürich
dc.rights.uri
http://rightsstatements.org/page/InC-NC/1.0/
dc.subject
HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK)
dc.subject
MIKROELEKTRONIK + INTEGRIERTE SCHALTUNGEN
dc.subject
GATE ARRAY SCHALTUNGEN (MIKROELEKTRONIK)
dc.subject
LAYOUTS/MIKROELEKTRONIK
dc.subject
VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS)
dc.subject
MICROELECTRONICS + INTEGRATED CIRCUITS
dc.subject
GATE ARRAYS CIRCUITS (MICROELECTRONICS)
dc.subject
LAYOUTS/MICROELECTRONICS
dc.title
Module generation in VLSI design
dc.type
Doctoral Thesis
dc.rights.license
In Copyright - Non-Commercial Use Permitted
ethz.title.subtitle
a graph theoretical approach
ethz.size
109 S.
ethz.code.ddc
DDC - DDC::6 - Technology, medicine and applied sciences::621.3 - Electric engineering
ethz.notes
Diss. Techn. Wiss. ETH Zürich, Nr. 8768, 1989. Ref.: W. Fichtner ; Korref.: M. Declercq.
ethz.identifier.diss
8768
ethz.identifier.nebis
000599219
ethz.publication.place
Zürich
ethz.publication.status
published
ethz.date.deposited
2017-06-13T00:53:57Z
ethz.source
ECOL
ethz.identifier.importid
imp593669d56c25582101
ethz.ecolpid
eth:38345
ethz.eth
yes
ethz.availability
Closed access
ethz.rosetta.installDate
2017-07-13T17:15:02Z
ethz.rosetta.lastUpdated
2020-02-14T22:19:37Z
ethz.rosetta.versionExported
true
ethz.COinS
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Doctoral Thesis [30094]