Show simple item record

dc.contributor.author
Gries, Matthias
dc.date.accessioned
2022-08-12T11:46:56Z
dc.date.available
2017-06-13T03:25:52Z
dc.date.available
2022-08-12T11:46:56Z
dc.date.issued
1999-04
dc.identifier.uri
http://hdl.handle.net/20.500.11850/145847
dc.identifier.doi
10.3929/ethz-a-004287257
dc.description.abstract
The functionality of volatile random access memories (RAMs) in personal computers, embedded systems, networking devices, and many other products is based on an access scheme which was designed over thirty years ago. Since then a variety of different realizations has evolved. Due to the fact that VLSI designs for memory chips have always been optimized for area and not for access speed, RAM chips have become more and more the performance bottleneck of complex computing systems. This survey gives an overview of current memory chip architectures. The basic functionality of memories is explained and the advantages and drawbacks of each RAM type are discussed. By providing a better understanding of the limits of current RAM designs, this report supports the decision for a particular RAM in an individual application.
en_US
dc.format
application/pdf
en_US
dc.language.iso
en
en_US
dc.publisher
ETH Zurich, Computer Engineering and Networks Laboratory
en_US
dc.rights.uri
http://rightsstatements.org/page/InC-NC/1.0/
dc.title
A survey of synchronous RAM architectures
en_US
dc.type
Report
dc.rights.license
In Copyright - Non-Commercial Use Permitted
ethz.journal.title
TIK Report
ethz.journal.volume
71
en_US
ethz.size
37 p.
en_US
ethz.code.ddc
DDC - DDC::0 - Computer science, information & general works::004 - Data processing, computer science
en_US
ethz.publication.place
Zurich
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02640 - Inst. f. Technische Informatik und Komm. / Computer Eng. and Networks Lab.
en_US
ethz.date.deposited
2017-06-13T03:26:43Z
ethz.source
ECOL
ethz.identifier.importid
imp59366a4a87fd369052
ethz.ecolpid
eth:24781
ethz.eth
yes
en_US
ethz.availability
Open access
en_US
ethz.rosetta.installDate
2017-07-19T01:08:20Z
ethz.rosetta.lastUpdated
2023-02-07T05:16:59Z
ethz.rosetta.versionExported
true
ethz.COinS
ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.atitle=A%20survey%20of%20synchronous%20RAM%20architectures&rft.jtitle=TIK%20Report&rft.date=1999-04&rft.volume=71&rft.au=Gries,%20Matthias&rft.genre=report&
 Search print copy at ETH Library

Files in this item

Thumbnail

Publication type

Show simple item record