3D exploration of Uniprocessor Schedules for DSP algorithms

Abstract

When implementing software for programmable digital signal processors (PDSPs), the design space is defined by a complex range of constraints and optimization objectives. Three implementation metrics that are crucial in many PDSP applications are the program memory requirement (code size), data memory requirement, and execution time. This paper addresses the problem of exploring the 3-dimensional space of trade-offs that is defined by these crucial metrics. Given a software library for a target PDSP, and a dataflow-based block diagram specification of a DSP application in terms of this library, our objective in this paper is to compute a full range of Pareto-optimal solutions. For solving this multi-objective optimization problem, an evolutionary algorithm based approach is applied, where two different Pareto-optimization methods are considered. We illustrate our techniques by analyzing the trade-off fronts of a practical application for a number of well-known, commercial PDSPs. Moreover, the two evolutionary Pareto-optimization methods are quantitatively compared on nine DSP applications.