System-level timing analysis and scheduling for embedded packet processors

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Author
Chakraborty, Samarjit
Date
2003
Type
    Doctoral Thesis
Rights / license
In Copyright - Non-Commercial Use Permitted
Permanent link
https://doi.org/10.3929/ethz-a-004613044
Publication status
published
External links
Search print copy at ETH Library
Contributors
Examiner: Ernst, Rolf
Examiner: Thiele, Lothar
Journal / series
Technische Informatik
Volume
054
Publisher
Institut für Technische Informatik und Kommunikationsnetze TIK, ETH Zürich
Subject
PROZESSVERWALTUNG + PROZESSMANAGEMENT (BETRIEBSSYSTEME); SCHEDULING (BETRIEBSSYSTEME); ECHTZEITSYSTEME + EINGEBETTETE SYSTEME (COMPUTERSYSTEME); PROCESS MANAGEMENT (OPERATING SYSTEMS); SCHEDULING (OPERATING SYSTEMS); REAL-TIME SYSTEMS + EMBEDDED SYSTEMS (COMPUTER SYSTEMS)
Organisational unit
03429 - Thiele, Lothar / Thiele, Lothar  
Notes
Diss., Technische Wissenschaften ETH Zürich, Nr. 15093, 2003.
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