Clock and data recovery circuit and clock synthesizers for 40 Gb/s high-density serial I/O-links in 90-nm CMOS

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Author
Bueren, Georg Paul Emil von
Date
2011
Type
    Doctoral Thesis
Rights / license
In Copyright - Non-Commercial Use Permitted
Permanent link
https://doi.org/10.3929/ethz-a-006696607
Publication status
published
External links
Search print copy at ETH Library
Contributors
Examiner: Jäckel, Heinz
Examiner: Leblebici, Yusuf
Publisher
ETH
Subject
SIGNALÜBERTRAGUNG + DATENKOMMUNIKATION (NACHRICHTENTECHNIK); DATENKOMMUNIKATION (COMPUTERSYSTEME); KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); SIGNAL TRANSMISSION + DATA COMMUNICATION (TELECOMMUNICATIONS); DATA COMMUNICATIONS (COMPUTER SYSTEMS); COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS)
Organisational unit
03386 - Jäckel, Heinz
Notes
Diss., Eidgenössische Technische Hochschule ETH Zürich, Nr. 19636, 2011.
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