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dc.contributor.author
Bueren, George von
dc.contributor.author
Barras, David
dc.contributor.author
Jäckel, Heinz
dc.contributor.author
Kromer, Christian
dc.contributor.author
Huber, Alex
dc.contributor.author
Kossel, Marcel
dc.date.accessioned
2017-06-08T22:05:20Z
dc.date.available
2017-06-08T22:05:20Z
dc.date.issued
2009
dc.identifier.isbn
1-4244-4354-7
dc.identifier.isbn
978-1-4244-4354-3
dc.identifier.other
10.1109/ESSCIRC.2009.5326023
dc.identifier.uri
http://hdl.handle.net/20.500.11850/16345
dc.language.iso
en
dc.publisher
IEEE
dc.subject
CMOS analog integrated circuits
dc.subject
jitter
dc.subject
phase locked loops
dc.subject
phase noise
dc.subject
voltage controlled oscillators
dc.title
Design and Phase Noise Analysis of a Multiphase 6 to 11 GHz PLL
dc.type
Conference Paper
ethz.book.title
Proceedings of the 2009 European Solid-State Circuits Conference
ethz.journal.title
Proceedings of ESSCIRC
ethz.pages.start
384
ethz.pages.end
387
ethz.event
35th European Solid-State Circuits Conference (ESSCIRC 2009)
ethz.event.location
Athens, Greece
ethz.event.date
September 14-18, 2009
ethz.publication.place
Piscataway, N.J.
ethz.publication.status
published
ethz.date.deposited
2017-06-08T22:05:41Z
ethz.source
ECIT
ethz.identifier.importid
imp59364c6339bc927602
ethz.ecitpid
pub:28215
ethz.eth
yes
ethz.availability
Metadata only
ethz.rosetta.installDate
2017-07-12T21:33:20Z
ethz.rosetta.lastUpdated
2017-12-21T12:58:46Z
ethz.rosetta.versionExported
true
ethz.COinS
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