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dc.contributor.author
de Fine Licht, Johannes
dc.contributor.supervisor
Larsen, Ken Friis
dc.contributor.supervisor
Hoefler, Torsten
dc.date.accessioned
2017-07-18T07:18:25Z
dc.date.available
2017-06-29T11:48:23Z
dc.date.available
2017-07-18T07:17:41Z
dc.date.available
2017-07-18T07:18:25Z
dc.date.issued
2016
dc.identifier.uri
http://hdl.handle.net/20.500.11850/167170
dc.description.abstract
This work investigates the potential of high performance computing (HPC) on fieldprogrammable gate arrays (FPGAs), highlighting concepts and programming techniques to pursue performance using high level synthesis (HLS) tools. We compute the peak single precision floating point performance on the AlphaData 7V3 board using a model of replicated processing elements, then implement a benchmark to verify the predicted performance in hardware, using both the SDAccel framework and a custom reference design provided by Xilinx. The benchmarks reach 302GOp/s and 548GOp/s on the two platforms, respectively. The techniques are applied to the field of stencil computations, proposing a temporally pipelined streaming design for the 2D Jacobian stencil that scales with available area on the chip, by using on-chip memory to buffer the incoming wavefront, achieving a sustained performance of 256GOp/s on a 256 × 256 grid. Finally the current state of FPGAs is discussed based on the results obtained, and comments are made on the future of reconfigurable computing in HPC.
en_US
dc.language.iso
en
en_US
dc.publisher
University of Copenhagen, Department of Computer Science
en_US
dc.title
Modeling and Implementing High Performance Programs on FPGA
en_US
dc.type
Master Thesis
ethz.publication.place
Copenhagen
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02150 - Dep. Informatik / Dep. of Computer Science::02666 - Institut für Hochleistungsrechnersysteme / Inst. f. High Performance Computing Syst::03950 - Hoefler, Torsten / Hoefler, Torsten
en_US
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02150 - Dep. Informatik / Dep. of Computer Science::02666 - Institut für Hochleistungsrechnersysteme / Inst. f. High Performance Computing Syst::03950 - Hoefler, Torsten / Hoefler, Torsten
en_US
ethz.date.deposited
2017-06-29T11:48:24Z
ethz.source
FORM
ethz.eth
no
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2017-07-18T07:17:44Z
ethz.rosetta.lastUpdated
2017-07-18T07:18:27Z
ethz.rosetta.exportRequired
true
ethz.rosetta.versionExported
true
ethz.COinS
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