Suppression of gate-induced drain leakage by optimization of junction profiles in 22 nm and 32 nm SOI nFETs

Metadata only

Author

Date

2010

Type

Conference Paper

ETH Bibliography

yes

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Publication status

published

External links

Journal / series

Solid-State Electronics

Volume

54(2)

Pages / Article No.

115 - 122

Publisher

Elsevier

Event

5th Workshop of the Thematic-Network-on-Silicon-on-Insulator-Technology-Devices-and-Circuits (EUROSOI 2009), Göteborg, Sweden, January 19-21, 2009

Subject

TCAD; Simulation; Gate induced drain leakage; Non-local band-to-band tunneling; High-K gate stacks; DGSOI; SGSOI; 22 nm technology node

Organisational unit

03228 - Fichtner, Wolfgang

Notes

Received 23 April 2009, Revised 11 June 2009, Accepted 21 August 2009, Available online 29 December 2009.

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yes

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