Analysis and Comparative Evaluation of Stacked-Transistor Half-Bridge Topologies Implemented with 14 nm Bulk CMOS Technology

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Autor(in)
Bezerra, Pedro A.M.
Khaddam-Aljameh, Riduan
Krismer, Florian
Kolar, Johann W.cc
Sridhar, Arvind
Brunschwiler, Thomas
Toifl, Thomas
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Datum
2017
Typ
    Conference Paper
Rechte / Lizenz
In Copyright - Non-Commercial Use Permitted
Persistenter Link
https://doi.org/10.3929/ethz-b-000187492
Publikationsstatus
published
Externe Links
Buchtitel
2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL)
Seiten / Artikelnummer
8013307
Verlag
IEEE
Konferenz
2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL), Stanford, CA, USA, July 9-12, 2017
Thema
IVR; CMOS; Stacked transistors; Half-bridge; Multiphase; 14 nm technology
Organisationseinheit
03573 - Kolar, Johann W. (emeritus) / Kolar, Johann W. (emeritus)  
Förderung
619488 - Manufacturing of Modular Interposer providing scalable Heat Removal, Power Delivery and Optical Signaling (EC)
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Zitate
4 Zitate in Scopus
ETH Bibliographie
yes
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