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dc.contributor.author
Schweizer, Mario
dc.contributor.author
Lizama, Ignacio
dc.contributor.author
Friedli, Thomas
dc.contributor.author
Kolar, Johann W.
dc.date.accessioned
2019-03-19T07:31:00Z
dc.date.available
2017-10-25T08:25:37Z
dc.date.available
2018-02-08T13:29:32Z
dc.date.available
2019-03-19T07:31:00Z
dc.date.issued
2010
dc.identifier.isbn
978-1-4244-5225-5
en_US
dc.identifier.isbn
978-1-4244-5226-2
en_US
dc.identifier.other
10.1109/iecon.2010.5674994
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/200229
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.title
Comparison of the Chip Area Usage of 2-Level and 3-Level Voltage Source Converter Topologies
en_US
dc.type
Conference Paper
dc.date.published
2010-12-23
ethz.book.title
IECON 2010 - 36th Annual Conference on IEEE Industrial Electronics Society
en_US
ethz.pages.start
391
en_US
ethz.pages.end
396
en_US
ethz.event
36th Annual Conference on IEEE Industrial Electronics Society (IECON 2010)
en_US
ethz.event.location
Glendale, AZ, USA
en_US
ethz.event.date
November 7-10, 2010
en_US
ethz.publication.place
Piscataway, NJ
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::03573 - Kolar, Johann W. / Kolar, Johann W.
en_US
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::03573 - Kolar, Johann W. / Kolar, Johann W.
en_US
ethz.date.deposited
2017-10-25T08:25:38Z
ethz.source
FORM
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2018-02-08T13:29:36Z
ethz.rosetta.lastUpdated
2019-03-19T07:31:25Z
ethz.rosetta.exportRequired
false
ethz.rosetta.versionExported
true
ethz.COinS
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