HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA

Open access
Date
2017-10Type
- Conference Paper
ETH Bibliography
yes
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Abstract
Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard
host processor with programmable manycore accelerators (PMCAs)
to combine general-purpose computing with domain-specific, efficient
processing capabilities. While leading companies successfully advance
their HESoC products, research lags behind due to the challenges of building
a prototyping platform that unites an industry-standard host processor
with an open research PMCA architecture.
In this work we introduce HERO, an FPGA-based research platform
that combines a PMCA composed of clusters of RISC-V cores, implemented
as soft cores on an FPGA fabric, with a hard ARM Cortex-A
multicore host processor. The PMCA architecture mapped on the FPGA
is silicon-proven, scalable, configurable, and fully modifiable. HERO includes
a complete software stack that consists of a heterogeneous crosscompilation
toolchain with support for OpenMP accelerator programming,
a Linux driver, and runtime libraries for both host and PMCA.
HERO is designed to facilitate rapid exploration on all software and hardware
layers: run-time behavior can be accurately analyzed by tracing
events, and modifications can be validated through fully automated hardware
and software builds and executed tests. We demonstrate the usefulness
of HERO by means of case studies from our research. Show more
Permanent link
https://doi.org/10.3929/ethz-b-000219249Publication status
publishedBook title
Proceedings of Computer Architecture Research with RISC-V Workshop (CARRV' 17)Publisher
CARRVEvent
Subject
Heterogeneous SoCs; Multicore ArchitecturesOrganisational unit
03996 - Benini, Luca / Benini, Luca
Funding
688860 - High-Performance Embedded Real-time Architectures for Low-Power Many-Core Systems (SBFI)
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ETH Bibliography
yes
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