Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications

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Author
Schiavone, Pasquale D.
Conti, Francesco
Rossi, Davide
Gautschi, Michael
Pullini, Antonio
Flamand, Eric
Benini, Luca
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Date
2017
Type
  • Conference Paper
Publication status
published
External links
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Book title
2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Pages / Article No.
8106976
Publisher
IEEE
Event
27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017), Thessaloniki, Greece, September 25-27, 2017
Subject
RISC-V; energy efficiency; area optimized; ultra-low-power; open-source; core; microprocessor; internet-of-things
Organisational unit
02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.
02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory
03996 - Benini, Luca / Benini, Luca  
Funding
162524 - MicroLearn: Micropower Deep Learning (SNF)
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