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dc.contributor.author
Lee, Donghyuk
dc.contributor.author
Khan, Samira
dc.contributor.author
Subramanian, Lavanya
dc.contributor.author
Ghose, Saugata
dc.contributor.author
Ausavarungnirun, Rachata
dc.contributor.author
Pekhimenko, Gennady
dc.contributor.author
Seshadri, Vivek
dc.contributor.author
Mutlu, Onur
dc.date.accessioned
2018-03-20T10:30:55Z
dc.date.available
2017-12-20T15:53:25Z
dc.date.available
2018-03-19T12:33:18Z
dc.date.available
2018-03-20T10:30:55Z
dc.date.issued
2017-06
dc.identifier.other
10.1145/3084464
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/223783
dc.description.abstract
Variation has been shown to exist across the cells within a modern DRAM chip. Prior work has studied and exploited several forms of variation, such as manufacturing-process- or temperature-induced variation. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the design and placement of different components in the DRAM chip: different regions in DRAM, based on their relative distances from the peripheral structures, require different minimum access latencies for reliable operation. In particular, we show that in most real DRAM chips, cells closer to the peripheral structures can be accessed much faster than cells that are farther. We call this phenomenon design-induced variation in DRAM. Our goals are to i) understand design-induced variation that exists in real, state-of-the-art DRAM chips, ii) exploit it to develop low-cost mechanisms that can dynamically find and use the lowest latency at which to operate a DRAM chip reliably, and, thus, iii) improve overall system performance while ensuring reliable system operation. To this end, we first experimentally demonstrate and analyze designed-induced variation in modern DRAM devices by testing and characterizing 96 DIMMs (768 DRAM chips). Our characterization identifies DRAM regions that are vulnerable to errors, if operated at lower latency, and finds consistency in their locations across a given DRAM chip generation, due to design-induced variation. Based on our extensive experimental analysis, we develop two mechanisms that reliably reduce DRAM latency. First, DIVA Profiling uses runtime profiling to dynamically identify the lowest DRAM latency that does not introduce failures. DIVA Profiling exploits design-induced variation and periodically profiles only the vulnerable regions to determine the lowest DRAM latency at low cost. It is the first mechanism to dynamically determine the lowest latency that can be used to operate DRAM reliably. DIVA Profiling reduces the latency of read/write requests by 35.1%/57.8%, respectively, at 55°C. Our second mechanism, DIVA Shuffling, shuffles data such that values stored in vulnerable regions are mapped to multiple error-correcting code (ECC) codewords. As a result, DIVA Shuffling can correct 26% more multi-bit errors than conventional ECC. Combined together, our two mechanisms reduce read/write latency by 40.0%/60.5%, which translates to an overall system performance improvement of 14.7%/13.7%/13.8% (in 2-/4-/8-core systems) across a variety of workloads, while ensuring reliable operation.
en_US
dc.language.iso
en
en_US
dc.publisher
ACM
en_US
dc.title
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms
en_US
dc.type
Conference Paper
ethz.book.title
Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS 2017)
en_US
ethz.journal.volume
1
en_US
ethz.journal.issue
2
en_US
ethz.pages.start
26
en_US
ethz.size
36
en_US
ethz.event
ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS 2017)
en_US
ethz.event.location
Urbana-Champaign, Il, USA
en_US
ethz.event.date
June 5-9, 2017
en_US
ethz.publication.place
New York, NY, USA
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02150 - Dep. Informatik / Dep. of Computer Science::02666 - Institut für Hochleistungsrechnersysteme / Inst. f. High Performance Computing Syst::09483 - Mutlu, Onur / Mutlu, Onur
en_US
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02150 - Dep. Informatik / Dep. of Computer Science::02666 - Institut für Hochleistungsrechnersysteme / Inst. f. High Performance Computing Syst::09483 - Mutlu, Onur / Mutlu, Onur
en_US
ethz.date.deposited
2017-12-20T15:53:25Z
ethz.source
FORM
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2018-04-01T10:10:37Z
ethz.rosetta.lastUpdated
2020-02-15T11:59:47Z
ethz.rosetta.versionExported
true
ethz.COinS
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