Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube
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Date
2017-01Type
- Journal Article
Publication status
publishedJournal / series
IEEE Transactions on Very Large Scale Integration (VLSI) SystemsVolume
Pages
Publisher
IEEESubject
3-D integration; Address scrambling; Cycle accurate (CA) model; Interconnect design; Smart memory cube (SMC)Organisational unit
03996 - Benini, Luca
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