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dc.contributor.author
Pellizzoni, Rodolfo
dc.contributor.author
Schranzhofer, Andreas
dc.contributor.author
Chen, Jian-Jian
dc.contributor.author
Caccamo, Marco
dc.contributor.author
Thiele, Lothar
dc.date.accessioned
2017-06-09T08:37:34Z
dc.date.available
2017-06-09T08:37:34Z
dc.date.issued
2010-03
dc.identifier.isbn
978-1-4244-7054-9
dc.identifier.isbn
978-3-9810801-6-2
dc.identifier.uri
http://hdl.handle.net/20.500.11850/27968
dc.language.iso
en
dc.publisher
IEEE
dc.subject
ESD
dc.title
Worst Case Delay Analysis for Memory Interference in Multicore Systems
dc.type
Conference Paper
ethz.book.title
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 : 8 - 12 March 2010, Dresden, Germany ; proceedings
ethz.pages.start
741
ethz.pages.end
746
ethz.event
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
ethz.event.location
Dresden, Germany
ethz.event.date
March 8-12, 2010
ethz.notes
Date of Current Version 29 April 2010.
ethz.publication.place
Piscataway, NJ
ethz.publication.status
published
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02640 - Inst. f. Technische Informatik und Komm. / Computer Eng. and Networks Lab.::03429 - Thiele, Lothar / Thiele, Lothar
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02640 - Inst. f. Technische Informatik und Komm. / Computer Eng. and Networks Lab.::03429 - Thiele, Lothar / Thiele, Lothar
ethz.date.deposited
2017-06-09T08:37:53Z
ethz.source
ECIT
ethz.identifier.importid
imp59364d821c9d115732
ethz.ecitpid
pub:46979
ethz.eth
yes
ethz.availability
Metadata only
ethz.rosetta.installDate
2017-07-12T22:55:25Z
ethz.rosetta.lastUpdated
2018-10-01T10:43:40Z
ethz.rosetta.versionExported
true
ethz.COinS
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