Bellasi, David E.
- Doctoral Thesis
Rights / licenseIn Copyright - Non-Commercial Use Permitted
The vision of the Internet of things (IoT) entails the connection of all possible objects to the Internet for the purpose of monitoring and actuation, and its realization requires sensing devices that are highly optimized in terms of performance, size, cost, and energy-efficiency. The IoT is one of the main drivers for the exponential growth of the number of wireless electronic devices produced and sold worldwide. To ensure the economic and ecologic feasibility of the IoT, in addition to the improvement of known techniques to acquire, process, and communicate information, the pursuit of innovative and unconventional methods is needed. Compressive sensing (CS) was proposed as a groundbreaking signal acquisition method that fuses sampling and compression in a single procedure, and thereby potentially reduces the energy cost of both acquisition and transmission of information with respect to the conventional combination of Nyquist-rate sampling and digital data compression. The theory of CS---due to much excited research activity in the past years---has reached a certain maturity, whereas the knowledge about the performance and limitations of CS in practical applications and under real-world conditions is still fragmentary and not well consolidated. The goal of this thesis is the quantitative assessment of the quality/compression trade-off, the hardware complexity and power consumption of CS-based signal acquisition systems for typical low-rate IoT sensor applications, such as biomedical and environmental monitoring. Related work in the field was primarily concerned with demonstrating the potential of CS with respect to conventional signal acquisition producing uncompressed data. In contrast, in this thesis the performance of CS techniques is confronted with the performance of well-established conventional compression techniques under realistic conditions. The investigation is conducted empirically, analyzing compressive sensor systems based not only on mathematical models but based on measurement results from fabricated prototypes of integrated mixed-signal sensor systems. In the first part of this thesis, the theory of CS is reviewed with emphasis on theoretical bounds relevant for its practical application, limitations are identified, and possible remedies are proposed. The advantages and disadvantages of different CS signal acquisition modalities based on analog or digital signal processing are contemplated---both on theoretical and empirical grounds---and the difference between them in terms of quality/compression trade-off is quantified. In a second part, mathematical power estimation models for compressive sensors are developed and employed to quantify the energy-efficiency of different compressive sensor architectures. The scope of the discussion is extended from the confrontation of different CS implementations to the comparison of CS-based and conventional compression methods on the system-level of abstraction. The subject of a third part is the empirical verification of the observations and results of the first two parts in the context of two application case studies which are biomedical signal acquisition for healthcare applications and current sensing for building and industrial monitoring. Both case studies revolve around corresponding prototypes of mixed-signal compressive sensor system-on-chips (SoCs) that allow physical measurements and performance tests to be conducted under real-world conditions. The prototypes are an 8-channel compressive biomedical signal acquisition SoC fabricated in a 130nm CMOS technology, and a compressive current sensing SoC realized in a 160nm CMOS technology. In the last part of this thesis, an innovative idea---called Transient Clocking---aimed at improving the energy-efficiency of the system toward the ultimate goal of energy-proportionality. Transient clocking denotes the attempt to operate a highly duty-cycled (sensor) system already during the power on transient phase, reducing its active on-time. To enable integrated compressive sensors to leverage the concept of transient clocking, an on-chip clock synthesizer based on a frequency-locked loop is designed. Two prototypes fabricated in a 65nm and in a 28nm CMOS technology are presented, and mark an important step toward energy-proportional sensor systems. Show more
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SubjectCompressive sensing (CS); Internet of things (IoT); wireless sensors; data compression; microelectronics; application specific integrated circuits (ASIC)
Organisational unit03996 - Benini, Luca / Benini, Luca
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