A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems

Metadata only

Author

Date

2018

Type

Conference Paper

ETH Bibliography

yes

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Publication status

published

External links

Book title

2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

Pages / Article No.

93 - 101

Publisher

IEEE

Event

24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2018), Vienna, Austria, May 13-16, 2018

Organisational unit

02533 - Institut für Neuroinformatik / Institute of Neuroinformatics

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ETH Bibliography

yes

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Research Collection