A receiver/antenna co-design for a 1.5mJ per fix fully-integrated 10×10×6mm3 GPS logger
- Conference Paper
This paper presents an ultra-low-power (ULP) GPS logger system that features a custom miniaturized antenna co-designed with a GPS analog front-end (AFE) optimized for heavy duty-cycling and a 10×10×6mm 3 form-factor. The complete system includes a GPS AFE, processor, two custom 8Mb flash memory chips, custom antenna, and a 12mAh polymer Li-ion battery. An electrically small differential loop antenna (ka value of 0.24) is designed and all components are integrated on the top and bottom of the antenna in close proximity without degrading the antenna efficiency. In the sleep mode, the processor and the timer consume 50nW and in active mode it draws 12.5mW from a 1.2V supply. The AFE achieves a maximum conversion gain of 72dB, a noise figure of 2.2dB, and P1dB of -46dB. The blocker level that desensitizes the gain by 1dB is -6.1dBm at 1710MHz, one of the closest blockers near the GPS bands. The GPS logger achieves a 10dB SNR after correlation at an input power level of -125dBm. The logger is capable of storing data for 37 position fixes by streaming 10ms of received signal per fix to dual flash memories for later egress and post-processing. Show more
Book title2018 IEEE Custom Integrated Circuits Conference (CICC)
Pages / Article No.
Organisational unit09647 - Jang, Taekwang / Jang, Taekwang
MoreShow all metadata