Trap-aware compact modeling and power-performance assessment of III-V tunnel FET
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Date
2019-02-11Type
- Conference Paper
ETH Bibliography
yes
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Publication status
publishedExternal links
Book title
Proceedings of the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2018)Pages / Article No.
Publisher
IEEEEvent
Subject
III-V tunnel FET; compact modeling; SPICE simulation; device traps; logic circuits; power-performance metricsFunding
619509 - Energy Efficient Tunnel FET Switches and Circuits (EC)
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ETH Bibliography
yes
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