Trap-aware compact modeling and power-performance assessment of III-V tunnel FET

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Author
Xiang, Yang
Yakimets, Dmitry
Sant, Saurabh
Memisevic, Elvedin
Garcia Bardon, Marie
Verhulst, Anne S.
Parvais, Bertrand
Schenk, Andreas
Wernersson, Lars-Erik
Groeseneken, Guido
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Date
2019-02-11
Type
  • Conference Paper
Publication status
published
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Book title
Proceedings of the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2018)
Pages / Article No.
8640183
Publisher
IEEE
Event
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2018), Burlingame, CA, USA, October 15-18, 2018
Subject
III-V tunnel FET; compact modeling; SPICE simulation; device traps; logic circuits; power-performance metrics
Funding
619509 - Energy Efficient Tunnel FET Switches and Circuits (EC)
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