3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

Thumbnail
Metadata only
Author
Vandooren, Anne
Franco, Jacopo
Wu, Zhuoheng
Parvais, Bertrand
Witters, Liesbeth Johanna
Walke, Amey Mahadev
Li, Wei
Peng, Lan
Desphande, Veeresh
Bufler, Fabian M.
Rassoul, Nouredine
Hellings, Geert
Jamieson, Geraldine
Inoue, Fumihiro
Verbinnen, Greet
Devriendt, Katia
Teugels, Lieve G.
Heylen, Nancy
Vecchio, Emma
Zheng, Tao
Rosseel, Erik
Vanherle, Wendy
Chan, Boon Teik
Hikavyy, Andriy Y.
Rítzenthaler, Romain
Besnard, Guillaume
Schwarzenbach, Walter
Gaudin, Gweltaz
Radu, Ionut
Nguyen, Bich Yen
Waldron, Niamh S.
De Heyn, Vincent
Mocuta, Dan M.
Collaert, Nadine
Show all
Date
2018-06
Type
    Conference Paper
Publication status
published
External links
Book title
2018 IEEE Symposium on VLSI Technology
Pages / Article No.
69 - 70
Publisher
IEEE
Event
38th IEEE Symposium on VLSI Technology, Honolulu, HI, USA, June 18-22, 2018
More
Show all metadata
Citations
Cited null times in Web of Science
Cited 9 times in Scopus
ETH Bibliography
yes
Altmetrics