Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm
dc.contributor.author
Buergin, Felix
dc.contributor.author
Carbognani, Flavio
dc.contributor.author
Hediger, Martin
dc.contributor.author
Meier, Hektor
dc.contributor.author
Meyer-Piening, Robert
dc.contributor.author
Santschi, Rafael
dc.contributor.author
Kaeslin, Hubert
dc.contributor.author
Felber, Norbert
dc.contributor.author
Fichtner, Wolfgang
dc.date.accessioned
2020-09-10T05:34:37Z
dc.date.available
2017-06-09T11:29:33Z
dc.date.available
2020-09-10T05:34:37Z
dc.date.issued
2006
dc.identifier.isbn
978-1-59593-381-2
en_US
dc.identifier.other
10.1145/1146909.1147054
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/36105
dc.description.abstract
This paper analyzes the power-area trade-off of functionally equivalent architectural implementations of a speech enhancement algorithm for hearing aids. Gate-level simulations and measurements show that an optimum degree of resource sharing (0.60mW in a 0.25μm CMOS process) is more energy-efficient than both the fully time-multiplexed (1.42mW) and the isomorphic architecture (1.54mW), without overly large area overhead (0.77mm2 against 0.43mm2 and 4.31mm2, respectively).
en_US
dc.language.iso
en
en_US
dc.publisher
Association for Computing Machinery
dc.subject
Hearing aids
en_US
dc.subject
Low-power architecture
en_US
dc.subject
Speech enhancement
en_US
dc.title
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm
en_US
dc.type
Conference Paper
ethz.book.title
DAC '06: Proceedings of the 43rd Annual Design Automation Conference
en_US
ethz.pages.start
558
en_US
ethz.pages.end
561
en_US
ethz.event
43rd Annual Design Automation Conference (DAC 2006)
en_US
ethz.event.location
San Francisco, CA, USA
ethz.event.date
July 24-28, 2006
en_US
ethz.identifier.wos
ethz.publication.place
New York, NY
ethz.publication.status
published
en_US
ethz.leitzahl
03228 - Fichtner, Wolfgang
en_US
ethz.leitzahl.certified
03228 - Fichtner, Wolfgang
ethz.date.deposited
2017-06-09T11:29:53Z
ethz.source
ECIT
ethz.identifier.importid
imp59364e1fe186a27272
ethz.ecitpid
pub:57693
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2017-07-18T10:09:40Z
ethz.rosetta.lastUpdated
2021-02-15T17:06:35Z
ethz.rosetta.exportRequired
true
ethz.rosetta.versionExported
true
ethz.COinS
ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.atitle=Low-power%20architectural%20trade-offs%20in%20a%20VLSI%20implementation%20of%20an%20adaptive%20hearing%20aid%20algorithm&rft.date=2006&rft.spage=558&rft.epage=561&rft.au=Buergin,%20Felix&Carbognani,%20Flavio&Hediger,%20Martin&Meier,%20Hektor&Meyer-Piening,%20Robert&rft.isbn=978-1-59593-381-2&rft.genre=proceeding&rft_id=info:doi/10.1145/1146909.1147054&rft.btitle=DAC%20'06:%20Proceedings%20of%20the%2043rd%20Annual%20Design%20Automation%20Conference
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Conference Paper [33140]