A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity
- Journal Article
Journal / seriesIEEE transactions on neural networks
Subjectaddress-event representation (AER); analog VLSI; integrate-and-fire (I & F) neurons; neuromorphic circuits; spike-based learning; spike-timing dependent plasticity (STDP)
Organisational unit03453 - Douglas, Rodney J.
NotesManuscript received 15 December 2004, Revised 11 May 2005.
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