A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity
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Date
2006-01Type
- Journal Article
ETH Bibliography
yes
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Publication status
publishedExternal links
Journal / series
IEEE Transactions on Neural NetworksVolume
Pages / Article No.
Publisher
IEEESubject
address-event representation (AER); analog VLSI; integrate-and-fire (I & F) neurons; neuromorphic circuits; spike-based learning; spike-timing dependent plasticity (STDP)Organisational unit
03453 - Douglas, Rodney J.
Notes
Manuscript received 15 December 2004, Revised 11 May 2005.More
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ETH Bibliography
yes
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