A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity

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Author
Indiveri, G.
Chicca, E.
Douglas, R.
Date
2006-01
Type
  • Journal Article
Publication status
published
External links
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Journal / series
IEEE Transactions on Neural Networks
Volume
17(1)
Pages / Article No.
211 - 221
Publisher
IEEE
Subject
address-event representation (AER); analog VLSI; integrate-and-fire (I & F) neurons; neuromorphic circuits; spike-based learning; spike-timing dependent plasticity (STDP)
Organisational unit
03453 - Douglas, Rodney J.  
Notes
Manuscript received 15 December 2004, Revised 11 May 2005.
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Citations
Cited 454 times in Web of Science
ETH Bibliography
yes
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