LLHD: A multi-level intermediate representation for hardware description languages
- Conference Paper
Modern Hardware Description Languages (HDLs) such as SystemVerilog or VHDL are, due to their sheer complexity, insufficient to transport designs through modern circuit design flows. Instead, each design automation tool lowers HDLs to its own Intermediate Representation (IR). These tools are monolithic and mostly proprietary, disagree in their implementation of HDLs, and while many redundant IRs exists, no IR today can be used through the entire circuit design flow. To solve this problem, we propose the LLHD multi-level IR. LLHD is designed as simple, unambiguous reference description of a digital circuit, yet fully captures existing HDLs. We show this with our reference compiler on designs as complex as full CPU cores. LLHD comes with lowering passes to a hardware-near structural IR, which readily integrates with existing tools. LLHD establishes the basis for innovation in HDLs and tools without redundant compilers or disjoint IRs. For instance, we implement an LLHD simulator that runs up to 2.4× faster than commercial simulators but produces equivalent, cycle-accurate results. An initial vertically-integrated research prototype is capable of representing all levels of the IR, implements lowering from the behavioural to the structural IR, and covers a sufficient subset of SystemVerilog to support a full CPU design. © 2020 ACM. Show more
Book titleProceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation
Pages / Article No.
PublisherAssociation for Computing Machinery
SubjectHardware description languages; intermediate representations; Transformation passes
Organisational unit03996 - Benini, Luca / Benini, Luca
NotesDue to the Corona virus (COVID-19) the conference was conducted virtually.
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